UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 759

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

3rd edition
Edition
Modification of description in (3) Option byte area and (5) On-chip debug
security ID setting area (
Modification of description in 3.1.2 Memory bank (
78F0537D only)
Addition of Note to Figure 3-14 Correspondence Between Data Memory and
Addressing (
Memory and Addressing (
Addition to description in 3.3 Instruction Address Addressing
Addition to description in 3.3.2 Immediate addressing
Addition to description in 3.3.3 Table indirect addressing
Addition to description in 3.4.3 Direct addressing
Modification of [Description example] in 3.4.4 Short direct addressing
Addition to description in 3.4.6 Register indirect addressing
Addition to description in 3.4.7 Based addressing
Addition to description in 3.4.8 Based indexed addressing
Addition of chapter
Modification of Table 5-1 Pin I/O Buffer Power Supplies
Addition of Caution to 5.2.1 Port 0
Modification of Figure 5-2 Block Diagram of P00
Modification of Figure 5-3 Block Diagram of P01
Modification of Figure 5-4 Block Diagram of P02
Modification of Figure 5-5 Block Diagram of P03, P05
Modification of Figure 5-6 Block Diagram of P04
Modification of Figure 5-7 Block Diagram of P06
Addition of Caution to 5.2.2 Port 1
Addition of description to 5.2.3 Port 2 and addition of Table 5-4 Setting Functions
of P20/ANI0 to P27/ANI7 Pins
Addition of Remark to and modification of Caution in 5.2.9 Port 12
Modification of Figure 5-22 Block Diagram of P120
Modification of Figure 5-23 Block Diagram of P121 to P124
Addition of a figure to Remark in 5.2.10 Port 13
Addition of (4) A/D port configuration register (ADPC) to 5.3 Registers
Controlling Port Function
Addition of Remark 2 and Notes 1 and 2 to Table 5-5 Settings of Port Mode
Register and Output Latch When Using Alternate Function (2/2)
µ
PD78F0536) and Figure 3-15 Correspondence Between Data
µ
PD78F0537D only) in 3.1.1
µ
PD78F0537, 78F0537D)
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
µ
PD78F0536, 78F0537, and
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 MEMORY
BANK SELECT
FUNCTION
(
AND 78F0537D ONLY)
CHAPTER 5 PORT
FUNCTIONS
µ
PD78F0536, 78F0537,
Chapter
(3/16)
759