UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 55

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
Common
area
Data memory
space
Bank
area
Program RAM area
Program
memory
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security
space
1 KB
RAM spcae in
which instruction
can be fetched
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
B F F F H
B C 0 0 H
B B F F H
8 4 F F H
8 3 F F H
7 F F F H
7 C 0 0 H
7 B F F H
0 7 F F H
0 3 F F H
8 0 0 0 H
0 4 0 0 H
0 0 0 0 H
When boot swap is used:
Setting).
Common
area
Bank
area
F E D F H
F E F F H
F E E 0 H
F A F F H
F F F F H
F F 0 0 H
F B 0 0 H
F 7 F F H
F 8 0 0 H
D F F F H
B F F F H
7 F F F H
C 0 0 0 H
8 0 0 0 H
E 0 0 0 H
0 0 0 0 H
Block 2FH
Block 20H
Block 1FH
Block 01H
Block 00H
(Memory bank 0)
Special function registers
Internal high-speed RAM
Internal expansion RAM
General-purpose
(memory bank 0)
32 x 8 bits
registers
Flash memory
Flash memory
1024 x 8 bits
6144 x 8 bits
16384 x 8 bits
32768 x 8 bits
256 x 8 bits
Reserved
Reserved
(SFR)
Figure 3-8. Memory Map ( PD78F0537D)
CHAPTER 3 CPU ARCHITECTURE
IDs to 0085H to 008EH.
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
User’s Manual U17260EJ6V0UD
Block 3FH
Block 30H
(Memory bank 1)
(Memory bank 2)
(Memory bank 1)
(Memory bank 4)
(Memory bank 3)
(Memory bank 5)
0 F F F H
0 0 8 F H
0 0 8 E H
7 F F F H
1 0 8 F H
1 0 8 E H
1 0 0 0 H
0 7 F F H
0 0 0 0 H
0 8 0 0 H
0 0 8 5 H
0 0 8 4 H
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
1 0 8 5 H
1 0 8 4 H
1 0 8 0 H
1 0 7 F H
Block 4FH
Block 40H
(Memory bank 2)
On-chip debug security
On-chip debug security
Option byte area
Option byte area
CALLT table area
Vector table area
CALLF entry area
ID setting area
ID setting area
Program area
Program area
1905 x 8 bits
Program area
2048 x 8 bits
64 x 8 bits
64 x 8 bits
5 x 8 bits
10 x 8 bits
5 x 8 bits
10 x 8 bits
. . .
Note1
Note1
Note1
Note1
1 F F F H
Block 7FH
Block 70H
(Memory bank 5)
Boot cluster 0
Boot cluster 1
Note2
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