UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 29

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
<R>
<R>
1.7 Outline of Functions
Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM
Internal
memory
Memory space
Main
system
clock
(oscillation
frequency)
Subsystem clock (oscillation
frequency)
Internal low-speed oscillation
clock (for TMH1,
WDT)
General-purpose registers
Minimum instruction execution time
Instruction set
I/O ports
2. Memory banks to be used can be changed using the bank select register (BANK).
capacity can be changed using the internal memory size switching register (IMS) and the internal
expansion RAM size switching register (IXS).
High-speed system
clock
Flash memory
(self-programming
supported)
High-speed RAM
Expansion RAM
Internal high-speed
oscillation clock
Item
Memory bank
Standard
products, (A)
grade products
(A2) grade
products
Standard
products, (A)
grade products
(A2) grade
products
Standard
products, (A)
grade products
(A2) grade
products
Standard
products, (A)
grade products
(A2) grade
products
Note 1
Note 1
Note 1
Note 2
µ
16 KB
768 bytes 1 KB
64 KB
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V
1 to 5 MHz: V
1 to 20 MHz: V
Internal oscillation
8 MHz (TYP.): V
8 MHz (TYP.): V
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): V
32.768 kHz (TYP.): V
Internal oscillation
240 kHz (TYP.): V
240 kHz (TYP.): V
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.1
0.25
122
• 8-bit operation, 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
Total:
CMOS I/O:
CMOS output:
N-ch open-drain I/O (6 V tolerance): 4
PD78F0531
µ
µ
s (high-speed system clock: @ f
µ
s (subsystem clock: @ f
s (TYP.) (internal high-speed oscillation clock: @ f
µ
24 KB
PD78F0532
User’s Manual U17260EJ6V0UD
DD
DD
DD
CHAPTER 1 OUTLINE
−
= 1.8 to 5.5 V
DD
DD
= 4.0 to 5.5 V, 1 to 10 MHz: V
= 4.0 to 5.5 V, 1 to 10 MHz: V
DD
DD
= 1.8 to 5.5 V
= 2.7 to 5.5 V
= 1.8 to 5.5 V
= 2.7 to 5.5 V
DD
DD
µ
32 KB
= 1.8 to 5.5 V
= 2.7 to 5.5 V
PD78F0533
−
SUB
= 32.768 kHz operation)
55
50
µ
48 KB
1 KB
PD78F0534
1
XH
= 20 MHz operation)
DD
DD
µ
60 KB
2 KB
PD78F0535
= 2.7 to 5.5 V,
= 2.7 to 5.5 V
RH
= 8 MHz (TYP.) operation)
µ
96 KB
4 banks
4 KB
PD78F0536
µ
128 KB
6 banks
6 KB
PD78F0537
µ
PD78F0537D
(1/2)
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