UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 731

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Controlling
high-speed
system
clock
Controlling
internal
high-speed
oscillation
clock
Controlling
subsystem
clock
Controlling
internal
low-speed
oscillation
clock
CPU clock
16-bit
timer/event
counters
00, 01
Function
X1 clock
External main
system clock
Main system
clock
High-speed
system clock
Internal high-
speed oscillation
clock
XT1/P123,
XT2/EXCLKS/
P124
XT1 clock,
external
subsystem clock
Subsystem clock
Internal low-
speed oscillation
clock
Details of
Function
−
−
Set the X1 clock after the supply voltage has reached the operable voltage of the
clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) to CHAPTER 32 ELECTRICAL SPECIFICATIONS
((A2) GRADE PRODUCTS: T
Do not change the value of EXCLK and OSCSEL while the external main system
clock is operating.
Set the external main system clock after the supply voltage has reached the
operable voltage of the clock to be used (see CHAPTER 29 ELECTRICAL
SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 32 ELECTRICAL
SPECIFICATIONS ((A2) GRADE PRODUCTS: T
If the high-speed system clock is selected as the main system clock, a clock other
than the high-speed system clock cannot be set as the peripheral hardware clock.
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In
addition, stop peripheral hardware that is operating on the high-speed system
clock.
Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In
addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock.
The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset
release.
Do not change the value of XTSTART, EXCLKS, and OSCSELS while the
subsystem clock is operating.
Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop
the watch timer if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
If “Internal low-speed oscillator cannot be stopped” is selected by the option byte,
oscillation of the internal low-speed oscillation clock cannot be controlled.
Set the clock after the supply voltage has reached the operable voltage of the
clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) to CHAPTER 32 ELECTRICAL SPECIFICATIONS
((A2) GRADE PRODUCTS: T
Selection of the main system clock cycle division factor (PCC0 to PCC2) and
switchover from the main system clock to the subsystem clock (changing CSS
from 0 to 1) should not be set simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock
cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to
the main system clock (changing CSS from 1 to 0).
When switching the internal high-speed oscillation clock to the high-speed system
clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can
be changed only once after a reset release.
The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin
at the same time, and the valid edge of TI011 and timer output (TO01) cannot be
used for the P06 pin at the same time. Select either of the functions.
If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control
register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the
captured data is undefined.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
A
A
= −40 to +125°C)).
= −40 to +125°C)).
Cautions
A
= −40 to +125°C)).
p. 161
p. 161
p. 161
p. 162
p. 163
p. 165
p. 165
pp. 165,
166
p. 166
p. 166
p. 167
pp. 169,
170, 172
p. 174
p. 175
p. 179
p. 179
Page
(5/25)
731