UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 208

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
(2) Operation in clear & start mode entered by TI00n pin valid edge input
208
(CR00n: compare register, CR01n: capture register)
This is an application example where the TO0n output level is inverted when the count value has been captured
& cleared.
The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is
detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated,
and the TO0n output level is inverted.
Remark n = 0:
Capture & count clear input
Compare match interrupt
TI00n pin
Count clock
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(TMC0n3, TMC0n2)
n = 0, 1:
TMC0n3, TMC0n2
Compare register
Capture interrupt
(TI00n pin input)
Capture register
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H
Operable bits
TM0n register
Operable bits
TO0n output
(INTTM00n)
(INTTM01n)
Capture signal
µ
µ
(CR00n)
(CR01n)
(CR00n: Compare Register, CR01n: Capture Register) (1/2)
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
0000H
detector
Edge
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(CR00n: Compare Register, CR01n: Capture Register)
00
0001H
0000H
Capture register
User’s Manual U17260EJ6V0UD
Timer counter
(CR01n)
(TM0n)
Compare register
Clear
M
(CR00n)
Match signal
10
M
N
N
controller
S
Output
S
TO0n output
Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
P
P
TO0n pin
Q
Q