UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 366

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
<R>
366
Address: FF56H After reset: 00H R/W
Notes 1.
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. f
Symbol
CKSR6
2.
3.
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
If the peripheral hardware clock (f
f
• V
• V
• V
If the peripheral hardware clock (f
= 0), when 1.8 V ≤ V
is prohibited.
Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 =
• PWM mode (TMC506 = 1)
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
PRS
TPS63
0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty
= 50%.
TMC501: Bit 1 of TMC50
PRS
7
0
0
0
0
0
0
0
0
0
1
1
1
1
DD
DD
DD
operating frequency varies depending on the supply voltage.
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
: Peripheral hardware clock frequency
Figure 15-8. Format of Clock Selection Register 6 (CKSR6)
TPS62
Other than above
6
0
0
0
0
0
1
1
1
1
0
0
0
0
DD
PRS
PRS
PRS
CHAPTER 15 SERIAL INTERFACE UART6
< 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: f
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
TPS61
5
0
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U17260EJ6V0UD
PRS
PRS
) operates on the internal high-speed oscillation clock (f
) operates on the high-speed system clock (f
TPS60
4
0
0
1
0
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
f
f
f
TM50 output
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
TPS63
Note 2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
3
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
3.906 kHz 9.77 kHz
1.953 kHz 4.88 kHz
2 MHz
f
PRS
Base clock (f
Note 3
=
TPS62
2
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz 625 kHz
156.25 kHz 312.5 kHz 625 kHz
5 MHz
f
PRS
XCLK6
=
) selection
TPS61
10 MHz
5 MHz
2.5 MHz
1.25 MHz
19.53 kHz 39.06 kHz
9.77 kHz
1
10 MHz
f
PRS
XH
) (XSEL = 1), the
Note 1
=
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
19.53 kHz
TPS60
20 MHz
RH
f
PRS
0
) (XSEL
=
PRS
)