UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 426

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

426
(2) IIC status register 0 (IICS0)
Address: FFAAH
Condition for clearing (EXC0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (ALD0 = 0)
• Automatically cleared after IICS0 is read
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Symbol
MSTS0
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation sets IICS0 to 00H.
Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
Remark
EXC0
IICS0
ALD0
0
1
0
1
0
1
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Extension code was not received.
Extension code was received.
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 35 CAUTIONS FOR WAIT.
MSTS0
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
<7>
Bit 7 of IIC control register 0 (IICC0)
After reset: 00H
Figure 17-6. Format of IIC Status Register 0 (IICS0) (1/3)
ALD0
<6>
CHAPTER 17 SERIAL INTERFACE IIC0
EXC0
<5>
Note
2
C.
User’s Manual U17260EJ6V0UD
R
Detection of extension code reception
COI0
<4>
Detection of arbitration loss
Master device status
Condition for setting (EXC0 = 1)
• When the higher four bits of the received address data is
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a “loss”.
either “0000” or “1111” (set at the rising edge of the
eighth clock).
TRC0
<3>
ACKD0
<2>
STD0
<1>
SPD0
<0>