XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 97

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.67 Clock Mask Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
BIT
6†
5†
4†
3†
2†
1†
0†
7
This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general
control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the clock
outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater than the power
required. See Table 4−41 for a complete description of the register contents.
RESET STATE
BIT NUMBER
CLOCK6_MASK
CLOCK5_MASK
CLOCK4_MASK
CLOCK3_MASK
CLOCK2_MASK
CLOCK1_MASK
CLOCK0_MASK
FIELD NAME
PCI register offset:
Register type:
Default value:
RSVD
ACCESS
7
0
RW
RW
RW
RW
RW
RW
RW
R
6
0
Table 4−41. Clock Mask Register Description
Reserved. Returns 0b when read.
Clock output 6 mask. This bit disables PCI bus CLKOUT6 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 5 mask. This bit disables PCI bus CLKOUT5 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 4 mask. This bit disables PCI bus CLKOUT4 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 3 mask. This bit disables PCI bus CLKOUT3 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 2 mask. This bit disables PCI bus CLKOUT2 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 1 mask. This bit disables PCI bus CLKOUT1 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
Clock output 0 mask. This bit disables PCI bus CLKOUT0 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
5
0
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
D9h
Read-only, Read/Write
00h
4
0
3
0
2
0
1
0
0
0
DESCRIPTION
Classic PCI Configuration Space
SCPS155C
87