XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 72

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
62
BIT
9
8
7
6
5
4
3
SCPS155C
FIELD NAME
PRI_DEC
SEC_DT
FBB_EN
VGA16
SRST
MAM
VGA
ACCESS
Table 4−17. Bridge Control Register Description (Continued)
RW
RW
RW
RW
RW
RW
R
Selects the number of PCI clocks that the bridge waits for a master on the secondary interface to
repeat a delayed transaction request. The counter starts once the delayed completion (the
completion of the delayed transaction on the primary interface) has reached the head of the
downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge
is ready to complete the delayed transaction with the initiating master on the secondary bus). If the
master does not repeat the transaction before the counter expires, then the bridge deletes the
delayed transaction from its queue and sets the discard timer status bit.
Primary discard timer. This bit has no meaning in PCI Express and is hardwired to 0b.
Fast back-to-back enable. This bit allows software to enable fast back-to-back transactions on the
secondary PCI interface.
Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the
bridge. Setting this bit causes the PRST terminal on the secondary interface to be asserted.
Master abort mode. This bit controls the behavior of the bridge when it receives a master abort or
an unsupported request.
VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O
addresses. This bit only has meaning if the VGA enable bit is set.
VGA enable. This bit modifies the response by the bridge to VGA compatible addresses. If this bit
is set, then the bridge decodes and forwards the following accesses on the primary interface to the
secondary interface (and, conversely, block the forwarding of these addresses from the secondary
to primary interface):
•
•
If this bit is set, then forwarding of VGA addresses is independent of the value of bit 2 (ISA), the I/O
address and memory address ranges defined by the I/O base and limit registers, the memory base
and limit registers, and the prefetchable memory base and limit registers of the bridge. The
forwarding of VGA addresses is qualified by bits 0 (IO_ENB) and 1 (MEMORY_ENB) in the
command register (offset 04h, see Section 4.3).
0 = The secondary discard timer counts 2 15 PCI clock cycles (default)
1 = The secondary discard timer counts 2 10 PCI clock cycles
0 = Fast back-to-back transactions are disabled (default)
1 = Secondary interface fast back-to-back transactions are enabled
0 = Secondary interface is not in reset state (default)
1 = Secondary interface is in the reset state
0 = Do not report master aborts. Returns FFFF FFFFh on reads and discards data on writes
1 = Respond with an unsupported request on PCI Express when a master abort is received on
0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default)
1 = Decode address bits [15:10] when decoding VGA I/O addresses
0 = Do not forward VGA compatible memory and I/O addresses from the primary to secondary
1 = Forward VGA compatible memory and I/O addresses (addresses defined above) from the
Memory accesses in the range 000A 0000h to 000B FFFFh
I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are 0000h) and
where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA
address aliases – address bits [15:10] may possess any value and are not used in the decoding)
(default).
PCI. Respond with target abort on PCI when an unsupported request completion on PCI
Express is received. This bit also enables error signaling on master abort conditions on
posted writes.
interface (addresses defined above) unless they are enabled for forwarding by the defined
I/O and memory address ranges (default)
primary interface to the secondary interface (if the I/O enable and memory enable bits are
set) independent of the I/O and memory address ranges and independent of the ISA enable
bit
DESCRIPTION
April 2007 Revised October 2008