XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 34

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3
3.1
3.1.1 Power-Up Sequence
24
SCPS155C
Feature/Protocol Descriptions
This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified
block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI
Express interface and the PCI bus interface is located at the bottom of the diagram.
Power-Up/-Down Sequencing
The bridge contains both 1.5-V and 3.3-V power terminals. In addition, a V
D3
requirements. The following power-up and power-down sequences describe how power is applied to these
terminals.
In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are fully
described in Section 3.2. The following power-up and power-down sequences describe how PERST is applied
to the bridge.
The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence
and is included in the following power-up and power-down descriptions.
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply V
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two
cold
delay requirements are satisfied:
−
−
state. The clamping voltage (V
Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit
satisfies the requirement for stable device clocks by the deassertion of PERST.
Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the deassertion of PERST.
Reset
Controller
Clock
Generator
Power
Mgmt
CCP
clamp voltage.
PCI Express
Transmitter
Figure 3−1. XIO2000A Block Diagram
CCP
PCI Bus Interface
) can be either 3.3-V or 5.0-V, depending on the PCI bus interface
Configuration and
Memory Register
PCI Express
Receiver
AUX
supply exists to support the
April 2007 Revised October 2008
Serial IRQ
Serial
EEPROM
GPIO