XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 108

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.3
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
98
31:21
11:5
BIT
20†
19†
18†
17†
16†
15†
14†
13†
12†
3:0
4†
SCPS155C
Uncorrectable Error Status Register
The uncorrectable error status register reports the status of individual errors as they occur on the primary PCI
Express interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5−2
for a complete description of the register contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
RX_OVERFLOW
ECRC_ERROR
CPL_TIMEOUT
PCI Express extended register offset:
Register type:
Default value:
FIELD NAME
CPL_ABORT
DLL_ERROR
UR_ERROR
FC_ERROR
UNXP_CPL
MAL_TLP
PSN_TLP
RSVD
RSVD
RSVD
Table 5−2. Uncorrectable Error Status Register Description
31
15
0
0
ACCESS
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
R
R
R
30
14
0
0
29
13
Reserved. Returns 000 0000 0000b when read.
Unsupported request error. This bit is asserted when an unsupported request is received.
Extended CRC error. This bit is asserted when an extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver overflow. This bit is asserted when the flow control logic detects that the transmitting
device has illegally exceeded the number of credits that were issued.
Unexpected completion. This bit is asserted when a completion packet is received that does
not correspond to an issued request.
Completer abort. This bit is asserted when the bridge signals a completer abort.
Completion time-out. This bit is asserted when no completion has been received for an issued
request before the time-out period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
Poisoned TLP. This bit is asserted when a poisoned TLP is received.
Reserved. Returns 000 0000b when read.
Data link protocol error. This bit is asserted if a data link-layer protocol error is detected.
Reserved. Returns 0h when read.
0
0
28
12
0
0
27
11
0
0
26
10
0
0
104h
Read-only, Read/Clear
0000h
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0