XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 117

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.13 Secondary Error Capabilities and Control Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
31:5
4:0†
BIT
The secondary error capabilities and control register allows the system to monitor and control the secondary
advanced error reporting capabilities. See Table 5−11 for a complete description of the register contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
SEC_FIRST_ERR
PCI Express extended register offset:
Register type:
Default value:
FIELD NAME
RSVD
Table 5−11. Secondary Error Capabilities and Control Register Description
31
15
0
0
ACCESS
RU
R
30
14
0
0
29
13
Reserved. Returns 000 0000 0000 0000 0000 0000 0000b when read.
First error pointer. This 5-bit value reflects the bit position within the secondary uncorrectable
error status register (offset 12Ch, see Section 5.10) corresponding to the class of the first error
condition that was detected.
0
0
28
12
0
0
27
11
0
0
26
10
0
0
138h
Read-only
0000 0000h
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
PCI Express Extended Configuration Space
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
SCPS155C
18
0
2
0
17
0
1
0
16
0
0
0
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