XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 91

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.61 Control and Diagnostic Register 0
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
31:24†
23:19†
15:14†
18:16
13:12
11:8†
5:4†
BIT
6†
3†
2†
1†
7
0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−35 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PRI_BUS_NUM
PREFETCH_4X
CFG_ACCESS
UP_REQ_BUF
UP_REQ_BUF
PRI_DEVICE_
RESET STATE
RESET STATE
FIELD NAME
BIT NUMBER
BIT NUMBER
_MEM_REG
PCI register offset:
Register type:
Default value:
_VALUE
_CTRL
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
NUM
ACCESS
31
15
Table 4−35. Control and Diagnostic Register 0 Description
RW
RW
RW
RW
RW
RW
RW
0
0
R
R
R
R
R
R
30
14
0
0
This field contains the captured primary bus number
This field contains the captured primary device number
Reserved. Returns 000b when read.
Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 00b.
Reserved. Returns 00b when read.
Reserved. Bits 11:8 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
Reserved. Returns 0b when read.
Prefetch 4X enable. This bit sets the prefetch behavior for upstream memory read multiple
transactions. If bit 24 (FORCE_MRM) in the general control register (offset D4h, see Section 4.65)
is set, then all upstream memory read transactions will prefetch the indicated number of cache lines.
If bit 19 (READ_PREFETCH_DIS) in the general control register (offset D4h, see Section 4.65) is
set, then this bit has no effect and only 1 DWORD will be fetched.
PCI upstream req−res buffer threshold value. The value in this field controls the buffer space that
must be available for the bridge to accept a PCI bus transaction. If the cache line size is not valid,
then the bridge will use 8 DW for calculating the threshold value
PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-res buffer
threshold control mode of the bridge.
Configuration access to memory-mapped registers. When this bit is set, the bridge allows
configuration access to memory-mapped configuration registers.
Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another mechanism,
the value written into this field must be 0b.
Reserved. Returns 0b when read.
0 = The bridge will prefetch up to 2 cache lines, as defined in the cache line size register (offset
1 = The bridge device will prefetch up to 4 cache lines, as defined in the cache line size register
00 = 1 Cacheline + 4 DW (default)
01 = 1 Cacheline + 8 DW
10 = 1 Cacheline + 12 DW
11 = 2 Cachelines + 4 DW
0 = PCI upstream req-res buffer threshold control mode disabled (default)
1 = PCI upstream req-res buffer threshold control mode enabled
29
13
0
0
0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions (default)
(offset 0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions.
C0h
Read/Write
0000 0000h
28
12
0
0
27
11
0
0
26
10
0
0
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
Classic PCI Configuration Space
20
0
4
0
19
0
3
0
SCPS155C
18
0
2
0
17
0
1
0
16
0
0
0
81