XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 54

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.10.3
44
Start
Start
S b6
S
SCPS155C
Figure 3−18 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the
slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment
is expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/W
command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the
slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no
acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a stop condition.
Figure 3−19 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The
serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes
are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,
the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after
a bridge master no acknowledge (logic high) followed by a stop condition.
A = Slave Acknowledgement
Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the
three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control
bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.
This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM
devices.
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3−13.
1
b5
Serial-Bus EEPROM Application
A = Slave Acknowledgement
0
Slave Address
b4
Slave Address
Data Byte 0
1
b3 b2 b1 b0
0
0
0
Figure 3−19. Serial-Bus Protocol—Multibyte Read
M
0
R/W
Figure 3−18. Serial-Bus Protocol—Byte Read
R/W
0
0
Data Byte 1
A
A
M = Master Acknowledgement
b7 b6 b5 b4 b3 b2 b1 b0
0
M = Master Acknowledgement
0
Word Address
0
M
Word Address
0
Data Byte 2
0
0
0
0
M
Restart
A
Restart
A
b7 b6
Data Byte 3
S
S/P = Start/Stop Condition
S
b6
S/P = Start/Stop Condition
1
b5
b5
0
Data Byte
Slave Address
b4
b4
Slave Address
April 2007 Revised October 2008
1
M
b3 b2 b1 b0
b3 b2 b1 b0
0
P
0
0
0
R/W
R/W
M
Stop
1
1
A
A
P