XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 133

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

6.11 Upstream Isochronous Window 2 Control Register
6.12 Upstream Isochronous Window 2 Base Address Register
6.13 Upstream Isochronous Window 2 Limit Register
April 2007 Revised October 2008
15:4
BIT
3:1
0
The upstream isochronous window 2 control register allows software to identify the TC associated with
upstream transactions targeting memory addresses in the range defined by the window. See Table 6−6 for
a complete description of the register contents.
The upstream isochronous window 2 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
The upstream isochronous window 2 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
ISOC_WINDOW_EN
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
FIELD NAME
RSVD
TC_ID
Table 6−6. Upstream Isochronous Window 2 Control Register Description
15
31
15
31
15
0
0
0
0
0
ACCESS
14
30
14
30
14
RW
RW
0
0
0
0
0
R
13
29
13
29
13
0
0
0
0
0
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are
12
28
12
28
12
0
0
0
0
0
applied to the appropriate TC
27
27
11
11
11
0
0
0
0
0
10
26
10
26
10
0
0
0
0
0
25
25
9
0
0
9
0
0
9
0
24
24
20h
Read-only, Read/Write
0000h
8
0
24h
Read/Write
0000 0000h
0
8
0
28h
Read/Write
0000 0000h
0
8
0
DESCRIPTION
23
23
Memory-Mapped TI Proprietary Register Space
7
0
0
7
0
0
7
0
22
22
6
0
0
6
0
0
6
0
21
21
5
0
0
5
0
0
5
0
20
20
4
0
0
4
0
0
4
0
19
19
3
0
0
3
0
0
3
0
SCPS155C
18
18
2
0
0
2
0
0
2
0
17
17
1
0
0
1
0
0
1
0
16
16
0
0
0
0
0
0
0
0
123