XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 113

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.8
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.9
April 2007 Revised October 2008
31:9
4:0†
BIT
8†
6†
7
5
Advanced Error Capabilities and Control Register
The advanced error capabilities and control register allows the system to monitor and control the advanced
error reporting capabilities. See Table 5−7 for a complete description of the register contents.
Header Log Register
The header log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW
TLP header). Each DWORD is stored with the least significant byte representing the earliest transmitted.
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
ECRC_CHK_CAPABLE
ECRC_GEN_CAPABLE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
PCI Express extended register offset:
Register type:
Default value:
PCI Express extended register offset:
Register type:
Default value:
ECRC_GEN_EN
ECRC_CHK_EN
FIELD NAME
FIRST_ERR
RSVD
Table 5−7. Advanced Error Capabilities and Control Register Description
31
15
31
15
0
0
0
0
ACCESS
30
14
30
14
0
0
0
0
RW
RW
RU
R
R
R
29
13
29
13
0
0
0
0
Reserved. Returns 000 0000 0000 0000 0000 0000b when read.
Extended CRC check enable
Extended CRC check capable. This read-only bit returns a value of 1b indicating that the
bridge is capable of checking extended CRC information.
Extended CRC generation enable
Extended CRC generation capable. This read-only bit returns a value of 1b indicating that
the bridge is capable of generating extended CRC information.
First error pointer. This 5-bit value reflects the bit position within the uncorrectable error
status register (offset 104h, see Section 5.3) corresponding to the class of the first error
condition that was detected.
28
12
28
12
0
0
0
0
0 = Extended CRC checking is disabled
1 = Extended CRC checking is enabled
0 = Extended CRC generation is disabled
1 = Extended CRC generation is enabled
27
27
11
11
0
0
0
0
26
10
26
10
0
0
0
0
118h
Read-only, Read/Write
0000 00A0h
11Ch, 120h, 124h, and 128h
Read-only
0000 0000h
25
25
0
9
0
0
9
0
24
24
0
8
0
0
8
0
DESCRIPTION
23
23
0
7
1
0
7
0
PCI Express Extended Configuration Space
22
22
0
6
0
0
6
0
21
21
0
5
1
0
5
0
20
20
0
4
0
0
4
0
19
19
0
3
0
0
3
0
SCPS155C
18
18
0
2
0
0
2
0
17
17
0
1
0
0
1
0
16
16
0
0
0
0
0
0
103