XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 126

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.26 VC Resource Status Register (VC1)
5.27 VC Arbitration Table
116
15:2
Phase 15
Phase 23
Phase 31
BIT
BIT
2:0
Phase 7
1
0
3
SCPS155C
The VC resource status register allows software to monitor the status of the port arbitration table for this VC.
See Table 5−22 for a complete description of the register contents.
The VC arbitration table is provided to allow software to define round-robin weighting for traffic targeting the
PCI Express port. The table is divided into 32 phases. See Table 5−24 for a complete description of the register
contents.
Each phase consists of a four-bit field as indicated below.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
FIELD NAME
VC_PENDING
PORT_TABLE
VC_ARB_ID
FIELD NAME
PCI Express extended register offset:
Register type:
Default value:
PCI Express extended register offset:
Register type:
Default value:
_STATUS
RSVD
RSVD
Phase 14
Phase 22
Phase 30
Phase 6
ACCESS
Table 5−22. VC Resource Status Register (VC1) Description
15
ACCESS
0
3
0
RW
R
Phase 13
Phase 21
Phase 29
RU
RU
Phase 5
R
Table 5−24. VC Arbitration Table Entry Description
14
0
2
0
Reserved. Returns 0b when read.
Virtual channel ID. This 3-bit field is used by software to identify the VC ID that must be allocated
this slot of arbitration bandwidth depending upon the VC arbitration scheme enabled. The default
value for this field is 000b.
Reserved. Returns 00 0000 0000 0000b when read.
VC negotiation pending. This bit is asserted when VC negotiation is in progress following a
request by software to enable the second VC.
Port arbitration table status. This bit is automatically set by hardware when any modification is
made to the port arbitration table entries for this VC within the extended configuration space.
This bit is cleared by hardware after software has requested a port arbitration table refresh and
the refresh has been completed.
13
0
1
0
Table 5−23. VC Arbitration Table
Phase 12
Phase 20
Phase 28
Phase 4
REGISTER FORMAT
12
0
0
0
11
0
Phase 11
Phase 19
Phase 27
10
Phase 3
0
176h
Read-only
0000h
180h – 18Ch
Read-only, Read/Write
0000 0000h
9
0
8
0
Phase 10
Phase 18
Phase 26
Phase 2
DESCRIPTION
DESCRIPTION
7
0
6
0
Phase 17
Phase 25
Phase 1
Phase 9
5
0
April 2007 Revised October 2008
4
0
Phase 16
Phase 24
Phase 0
Phase 8
3
0
2
0
OFFSET
1
0
18Ch
180h
184h
188h
0
0