XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 94

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.65 General Control Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
84
31:30†
22:20†
29:28
27†
26†
25†
24†
23†
BIT
SCPS155C
This read/write register controls various functions of the bridge. See Table 4−39 for a complete description
of the register contents.
LOW_POWER
PRIORITY_EN
ASPM_CTRL_
FORCE_MRM
FIELD NAME
CFG_RETRY
RESET STATE
RESET STATE
DEF_OVRD
BIT NUMBER
BIT NUMBER
VERSION_
PCI_PM_
POWER_
STRICT_
PCI register offset:
Register type:
Default value:
_CNTR
OVRD
RSVD
CTRL
_EN
ACCESS
RW
RW
RW
RW
RW
RW
RW
31
15
R
1
1
Table 4−39. General Control Register Description
30
14
0
1
Configuration retry counter. Configures the amount of time that a configuration request must be retried
on the secondary PCI bus before it may be completed with configuration retry status on the PCI
Express side.
Reserved. Returns 00b when read.
Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCI Express
TX drivers is enabled. The default for this bit is 0b.
PCI power management version control. This bit controls the value reported in bits 2:0 (PM_VERSION)
in the power management capabilities register (offset 52h, see Section 4.32). It also controls the value
of bit 3 (NO_SOFT_RESET) in the power management control/status register (offset 54h, see Section
4.33).
Strict priority enable. When this bit is set and bits 6:4 (LOW_PRIORITY_COUNT) in the port VC
capability register 1 (offset 154h, see Section 5.17) are 000b, meaning that strict priority VC arbitration
is used, the extended VC always receives priority over VC0 at the PCI Express port.
Force memory read multiple
Active state power management control default override. This bit determines the power-up default for
bits 1:0 (ASLPMC) of the link control register (offset A0h, see Section 4.53) in the PCI Express
capability structure.
Power override. This bit field determines how the bridge responds when the slot power limit is less
than the amount of power required by the bridge and the devices behind the bridge.
00 = 25 µs
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power Management 1.1
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power Management 1.2
0 = The default LOW_PRIORITY_COUNT is 001b
1 = The default LOW_PRIORITY_COUNT is 000b (default)
0 = Memory read multiple transactions are disabled (default)
1 = All upstream memory read transactions initiated on the PCI bus are treated as though they
0 = Power-on default indicates that active state power management is disabled (00b) (default)
1 = Power-on default indicates that active state power management is enabled for L0s and L1 (11b)
000 = Ignore slot power limit (default)
001 = Assert the PWR_OVRD terminal
010 = Disable secondary clocks selected by the clock mask register
011 = Disable secondary clocks selected by the clock mask register and assert the PWR_OVRD
100 = Respond with unsupported request to all transactions except for configuration transactions
101, 110, 111 = Reserved
29
13
0
0
compliance (default)
compliance
are memory read multiple transactions where prefetching is supported
terminal
(type 0 or type 1) and set slot power limit messages
D4h
Read-only, Read/Write
8206 C000h
28
12
0
0
27
11
0
0
26
10
0
0
25
1
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
1
2
0
17
1
1
0
16
0
0
0