XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 95

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
k
April 2007 Revised October 2008
18:16† L0s_LATENCY
15:13†
These bits are sticky and must retain their value when the bridge is powered by V AUX .
9:8†
7:0†
11
10
BIT
19†
12†
k
k
MIN_POWER_
MIN_POWER_
FIELD NAME
L1_LATENCY
PREFETCH_
VC_CAP_EN
BEACON_
BPCC_E
ENABLE
READ_
SCALE
VALUE
DIS
ACCESS
Table 4−39. General Control Register Description (Continued)
RW
RW
RW
RW
RW
RW
RW
RW
Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions.
L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the L0s
state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see Section
4.49).
L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the L1
state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see
Section 4.49).
VC capability structure enable. This bit enables the VC capability structure by changing the next
offset field of the advanced error reporting capability register at offset 102h.
Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are stopped
when the bridge is placed in the D3 state. It is assumed that if the secondary bus clocks are required
to be active, that a reference clock continues to be provided on the PCI Express interface.
Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link when in
L2.
Minimum power scale. This value is programmed to indicate the scale of bits 7:0
(MIN_POWER_VALUE).
Minimum power value. This value is programmed to indicate the minimum power requirements. This
value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum power
requirements for the bridge. The default is 00h, because this feature is only usable when the system
implementer adds the PCI devices’ power consumption to the bridge power consumption and
reprograms this field with an EEPROM or the system BIOS.
0 = Prefetch to the next cache line boundary on a burst read (default)
1 = Fetch only a single DWORD on a burst read
000 = Less than 64 ns
001 = 64 ns up to less than 128 ns
010 = 128 ns up to less than 256 ns
011 = 256 ns up to less than 512 ns
100 = 512 ns up to less than 1 µs
101 = 1 µs up to less than 2 µs
110 = 2 µs to 4 µs (default)
111 = More than 4 µs
000 = Less than 1 µs
001 = 1 µs up to less than 2 µs
010 = 2 µs up to less than 4 µs
011 = 4 µs up to less than 8 µs
100 = 8 µs up to less than 16 µs
101 = 16 µs up to less than 32 µs
110 = 32 µs to 64 µs (default)
111 = More than 64 µs
0 = VC capability structure disabled (offset field = 000h)
1 = VC capability structure enabled (offset field = 150h)
0 = Secondary bus clocks are not stopped in D3 (default)
1 = Secondary bus clocks are stopped on D3
0 = WAKE mechanism is used exclusively. Beacon is not used (default).
1 = Beacon and WAKE mechanisms are used
00 = 1.0x (default)
01 = 0.1x
10 = 0.01x
11 = 0.001x
DESCRIPTION
Classic PCI Configuration Space
SCPS155C
85