XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 136

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Memory-Mapped TI Proprietary Register Space
6.18 GPIO Data Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.19 Serial-Bus Data Register
126
15:8
BIT
7†
6†
5†
4†
3†
2†
1†
0†
SCPS155C
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default
value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. This
register is an alias of the GPIO data register in the classic PCI configuration space (offset B6h, see
Section 4.60). See Table 6−9 for a complete description of the register contents.
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register that initiates the bus cycle. When reading data
from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and
status register (offset 47h, see Section 6.22) is cleared. This register is an alias for the serial-bus data register
in the PCI header (offset B0h, see Section 4.55). This register is reset by a PCI Express reset (PERST), a
GRST, or the internally-generated power-on reset.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
FIELD NAME
GPIO7_Data
GPIO6_Data
GPIO5_Data
GPIO4_Data
GPIO3_Data
GPIO2_Data
GPIO1_Data
GPIO0_Data
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
RSVD
15
ACCESS
0
7
0
RW
RW
RW
RW
RW
RW
RW
RW
R
14
0
6
0
Table 6−9. GPIO Data Register Description
Reserved. Returns 00h when read.
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of
GPIO7 when in output mode.
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of
GPIO6 when in output mode.
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of
GPIO5 when in output mode.
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of
GPIO4 when in output mode.
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of
GPIO3 when in output mode.
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of
GPIO2 when in output mode.
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of
GPIO1 when in output mode.
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of
GPIO0 when in output mode.
13
0
5
0
12
0
4
0
11
0
3
0
10
0
2
0
9
0
1
0
8
0
42h
Read-only, Read/Write
00XXh
44h
Read/Write
00h
0
0
DESCRIPTION
7
x
6
x
5
x
April 2007 Revised October 2008
4
x
3
x
2
x
1
x
0
x