XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 107

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.1
5.2
April 2007 Revised October 2008
Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express advanced error reporting
capabilities. The register returns 0001h when read.
Next Capability Offset/Capability Version Register
This read-only register identifies the next location in the PCI Express extended capabilities link list. If bit 12
(VC_CAP_EN) in the general control register (offset D4h, see Section 4.65) is 0b, then the upper 12 bits in
this register are 000h, indicating the end of the linked list. If VC_CAP_EN is 1b, then the upper 12 bits in this
register are 150h, indicating the existance of the VC capability structure at offset 150h. The four least
significant bits identify the revision of the current capability block as 1h.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
PCI Express extended register offset:
Register type:
Default value:
PCI Express extended register offset:
Register type:
Default value:
Table 5−1. PCI Express Extended Configuration Register Map (Continued)
15
15
0
0
Port arbitration table for VC1 (phase 127 – phase 120)
Port arbitration table for VC1 (phase 111 – phase 104)
Port arbitration table for VC1 (phase 119 – phase 112)
Port arbitration table for VC1 (phase 103 – phase 96)
Port arbitration table for VC1 (phase 23 – phase 16)
Port arbitration table for VC1 (phase 31 – phase 24)
Port arbitration table for VC1 (phase 39 – phase 32)
Port arbitration table for VC1 (phase 47 – phase 40)
Port arbitration table for VC1 (phase 55 – phase 48)
Port arbitration table for VC1 (phase 63 – phase 56)
Port arbitration table for VC1 (phase 71 – phase 64)
Port arbitration table for VC1 (phase 79 – phase 72)
Port arbitration table for VC1 (phase 87 – phase 80)
Port arbitration table for VC1 (phase 95 – phase 88)
Port arbitration table for VC1 (phase 15 – phase 8)
Port arbitration table for VC1 (phase 7 – phase 0)
14
14
0
0
VC arbitration table (phase 31 − phase 24)
13
13
0
0
REGISTER NAME
12
12
0
x
Reserved
Reserved
11
11
0
0
10
10
0
x
100h
Read-only
102h
Read-only
0001h
XX01h
9
0
9
0
8
0
8
x
7
0
7
0
PCI Express Extended Configuration Space
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
SCPS155C
2
0
2
0
190h – 1BCh
200h – FFCh
OFFSET
1CCh
1DCh
18Ch
1C0h
1C4h
1C8h
1D0h
1D4h
1D8h
1ECh
1FCh
1E0h
1E4h
1E8h
1F0h
1F4h
1F8h
1
0
1
0
0
1
0
1
97