XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 118

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.14 Secondary Header Log Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.15 Virtual Channel Capability ID Register
108
127:64†
43:40†
39:36†
63:44
35:0
BIT
SCPS155C
The secondary header log register stores the transaction address and command for the PCI bus cycle that
led to the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h
accesses register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register
bits 127:96. See Table 5−12 for a complete description of the register contents.
This read-only register identifies the linked list item as the register for PCI Express VC capabilities. The register
returns 0002h when read.
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
TRANS_ATTRIBUTE
PCI Express extended register offset:
Register type:
Default value:
PCI Express extended register offset:
Register type:
Default value:
LOWER_CMD
UPPER_CMD
FIELD NAME
ADDRESS
RSVD
127
111
95
79
63
47
31
15
15
0
0
0
0
0
0
0
0
0
Table 5−12. Secondary Header Log Register Description
ACCESS
126
110
94
78
62
46
30
14
14
0
0
0
0
0
0
0
0
0
RU
RU
RU
R
R
125
109
93
77
61
45
29
13
13
0
0
0
0
0
0
0
0
0
Transaction address. The 64-bit value transferred on AD[31:0] during the first and second
address phases. The first address phase is logged to 95:64 and the second address phase
is logged to 127:96. In the case of a 32-bit address, bits 127:96 are set to 0000 0000h.
Reserved. Returns 00000h when read.
Transaction command upper. Contains the status of the C/BE terminals during the second
address phase of the PCI transaction that generated the error if using a dual-address cycle.
Transaction command lower. Contains the status of the C/BE terminals during the first
address phase of the PCI transaction that generated the error.
Transaction attribute. Because the bridge does not support the PCI-X attribute transaction
phase, these bits have no function, and return 0 0000 0000h when read.
124
108
92
76
60
44
28
12
12
0
0
0
0
0
0
0
0
0
123
107
91
75
59
43
27
11
11
0
0
0
0
0
0
0
0
0
122
106
90
74
58
42
26
10
10
0
0
0
0
0
0
0
0
0
13Ch, 140h, 144h, and 148h
Read-only
0000 0000h
150h
Read-only
0002h
121
105
89
73
57
41
25
0
0
0
0
0
0
0
9
0
9
0
120
104
88
72
56
40
24
0
0
0
0
0
0
0
8
0
8
0
DESCRIPTION
119
103
87
71
55
39
23
0
0
0
0
0
0
0
7
0
7
0
118
102
86
70
54
38
22
0
0
0
0
0
0
0
6
0
6
0
101
117
85
69
53
37
21
0
0
0
0
0
0
0
5
0
5
0
April 2007 Revised October 2008
116
100
84
68
52
36
20
0
0
0
0
0
0
0
4
0
4
0
115
99
83
67
51
35
19
0
0
0
0
0
0
0
3
0
3
0
114
98
82
66
50
34
18
0
0
0
0
0
0
0
2
0
2
0
113
97
81
65
49
33
17
0
0
0
0
0
0
0
1
0
1
1
112
96
80
64
48
32
16
0
0
0
0
0
0
0
0
0
0
0