XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 141

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.25 Serial IRQ Status Register
April 2007 Revised October 2008
BIT
BIT
3†
2†
1†
0†
15
14
13
12
10
11
9
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ
is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are
defined as edge mode in the serial IRQ edge control register are not reported in this status register.
This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h,
see Section 4.74). See Table 6−14 for a complete description of the register contents.
RESET STATE
BIT NUMBER
FIELD NAME
FIELD NAME
IRQ3_MODE
IRQ2_MODE
IRQ1_MODE
IRQ0_MODE
Device control memory window register offset:
Register type:
Default value:
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
Table 6−13. Serial IRQ Edge Control Register Description (Continued)
ACCESS
15
ACCESS
0
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RW
RW
RW
RW
Table 6−14. Serial IRQ Status Register Description
14
0
IRQ 15 asserted. This bit indicates that the IRQ has been asserted.
IRQ 14 asserted. This bit indicates that the IRQ has been asserted.
IRQ 13 asserted. This bit indicates that the IRQ has been asserted.
IRQ 12 asserted. This bit indicates that the IRQ has been asserted.
IRQ 11 asserted. This bit indicates that the IRQ has been asserted.
IRQ 10 asserted. This bit indicates that the IRQ has been asserted.
IRQ 9 asserted. This bit indicates that the IRQ has been asserted.
IRQ 3 edge mode
IRQ 2 edge mode
IRQ 1 edge mode
IRQ 0 edge mode
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
13
0
0 = Edge mode (default)
1 = Level mode
0 = Edge mode (default)
1 = Level mode
0 = Edge mode (default)
1 = Level mode
0 = Edge mode (default)
1 = Level mode
12
0
11
0
10
0
9
0
4Ch
Read/Clear
0000h
8
0
DESCRIPTION
DESCRIPTION
Memory-Mapped TI Proprietary Register Space
7
0
6
0
5
0
4
0
3
0
SCPS155C
2
0
1
0
0
0
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