XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 75

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.33 Power Management Control/Status Register
4.34 Power Management Bridge Support Extension Register
April 2007 Revised October 2008
14:13
12:9
BIT
BIT
7:4
1:0
5:0
15
8
3
2
7
6
This register determines and changes the current power state of the bridge. No internal reset is generated
when transitioning from the D3
register contents.
This read-only register indicates to host software what the state of the secondary bus will be when the bridge
is placed in D3. See Table 4−20 for a complete description of the register contents.
RESET STATE
NO_SOFT_RESET
RESET STATE
BIT NUMBER
BIT NUMBER
FIELD NAME
PCI register offset:
Register type:
Default value:
DATA_SCALE
PCI register offset:
Register type:
Default value:
FIELD NAME
PWR_STATE
BSTATE
PME_STAT
DATA_SEL
BPCC
RSVD
PME_EN
Table 4−20. Power Management Bridge Support Extension Register Description
RSVD
RSVD
Table 4−19. Power Management Control/Status Register Description
ACCESS
15
0
7
0
R
R
R
ACCESS
RW
RW
R
R
R
R
R
R
14
0
6
1
Bus power/clock control enable. This bit indicates to the host software if the bus secondary clocks
are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled by bit 11
(BPCC_E) in the general control register (offset D4h, see Section 4.65).
B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.
Reserved. Returns 00 0000b when read.
0 = The secondary bus clocks are not stopped in D3
1 = The secondary bus clocks are stopped in D3
13
PME status. This bit is read-only and returns 0b when read.
Data scale. This 2-bit field returns 00b when read since the bridge does not use the data
register.
Data select. This 4-bit field returns 0h when read since the bridge does not use the data
register.
PME enable. This bit has no function and acts as scratchpad space. The default value for this
bit is 0b.
Reserved. Returns 0h when read.
No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset D4h,
see Section 4.65) is 0b, then this bit returns 0b for compatibility with version 1.1 of the PCI
Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, then this bit returns 1b
indicating that no internal reset is generated and the device retains its configuration context
when transitioning from the D3 hot state to the D0 state.
Reserved. Returns 0b when read.
Power state. This 2-bit field determines the current power state of the function and sets the
function into a new power state. This field is encoded as follows:
0
5
0
hot
00 = D0 (default)
01 = D1
10 = D2
11 = D3 hot
54h
Read-only, Read/Write
0000h
56h
Read-only
40h
state to the D0 state. See Table 4−19 for a complete description of the
12
0
4
0
11
0
3
0
10
0
2
0
9
0
1
0
8
0
DESCRIPTION
0
0
DESCRIPTION
7
0
6
0
5
0
Classic PCI Configuration Space
4
0
3
0
SCPS155C
2
0
1
0
0
0
65