XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 32

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Introduction
22
CLKRUN_EN
EXT_ARB_EN
GPIO0 //
CLKRUN
GPIO1 //
PWR_OVRD
GPIO2
GPIO3
GPIO4 // SCL
SIGNAL
SCPS155C
BALL
GZZ/
ZZZ
U05
U06
R07
B15
A15
T05
T06
BALL
ZHC
M04
M05
B13
C12
P03
N04
P04
BALL
ZHH
N04
M04
B13
B12
P03
P04
P05
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
Table 2−12. Miscellaneous Terminals
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CELL
TYPE
LV
LV
LV
LV
LV
LV
LV
CLAMP
V DD_33
V DD_33
V DD_33
V DD_33
V DD_33
V DD_33
V DD_33
RAIL
EXTERNAL
Optional
Optional
Optional
Optional
PARTS
resistor
resistor
resistor
resistor
pullup
pullup
pullup
pullup
−
−
−
Clock run enable
0 = Clock run support disabled
1 = Clock run support enabled
Note: The CLKRUN_EN input buffer has an internal
active pulldown.
External arbiter enable
0 = Internal arbiter enabled
1 = External arbiter enabled
Note: The EXT_ARB_EN input buffer has an internal
active pulldown.
General-purpose I/O 0/clock run. This terminal
functions as a GPIO controlled by bit 0 (GPIO0_DIR)
in the GPIO control register (see Section 4.59) or the
clock run terminal. This terminal is used as clock run
input when the bridge is placed in clock run mode.
Note: In clock run mode, an external pullup resistor
is required to prevent the CLKRUN signal from
floating.
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 1/power override. This terminal
functions as a GPIO controlled by bit 1 (GPIO1_DIR)
in the GPIO control register (see Section 4.59) or the
power override output terminal. GPIO1 becomes
PWR_OVRD when bits 22:20 (POWER_OVRD) in
the general control register are set to 001b or 011b
(see Section 4.65).
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 2. This terminal functions as a
GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO
control register (see Section 4.59).
Note: When PERST is deasserted, this terminal must
be a 1b to enable the PCI Express 1.0a compatibility
mode.
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 3. This terminal functions as a
GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO
control register (see Section 4.59).
Note: This terminal has an internal active pullup
resistor.
GPIO4 or serial-bus clock. This terminal functions as
serial-bus clock if a pullup resistor is detected on
SDA. If a pulldown resistor is detected on SDA, this
terminal functions as GPIO4.
Note: In serial-bus mode, an external pullup resistor
is required to prevent the SCL signal from floating.
Note: This terminal has an internal active pullup
resistor.
DESCRIPTION
April 2007 Revised October 2008