XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet
XIO2000AI
Available stocks
Related parts for XIO2000AI
XIO2000AI Summary of contents
Page 1
... XIO2000A/XIO2000AI PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS155C April 2007 Revised October 2008 Printed on Recycled Paper ...
Page 2
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...
Page 3
Section 1 XIO2000A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 4 Classic PCI Configuration Space 4.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Device Capabilities Register 4.50 Device Control Register 4.51 Device Status Register 4.52 Link Capabilities Register 4.53 Link Control Register . . . . . . . . . . . . . . . . . . . . ...
Page 6
Contents 5.23 VC Resource Status Register (VC0) 5.24 VC Resource Capability Register (VC1) 5.25 VC Resource Control Register (VC1) 5.26 VC Resource Status Register (VC1) 5.27 VC Arbitration Table . . . . . . . . . . . ...
Page 7
Figure 2−1 XIO2000A GZZ/ZZZ MicroStar BGA 2−2 XIO2000A ZHH Microstar BGA Package (Bottom View) 3−1 XIO2000A Block Diagram . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Tables Table 2−1 XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically 2−2 XIO2000A ZHH Terminals Sorted Alphanumerically 2−3 XIO2000A Signal Names Sorted Alphabetically 2−4 Power Supply Terminals . . . . . . . . . . . . . . . . ...
Page 9
Table 4−22 MSI Message Lower Address Register Description 4−23 MSI Message Data Register Description 4−24 PCI Express Capabilities Register Description 4−25 Device Capabilities Register Description 4−26 Device Control Register Description 4−27 Device Status Register Description 4−28 Link Capabilities Register Description ...
Page 10
Tables Table 5−22 VC Resource Status Register (VC1) Description 5−23 VC Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
... Masters with Internal Configurable, 2-Level Prioritization Scheme D Low Power Design (<350 mW) Ensures Ease of Implementation D XIO2000AI Supports Industrial Temperatures at 33-MHz Bus Speeds Table 1−1. Figure 1−1. MicroStar BGA is a trademark of Texas Instruments. Other trademarks are the property of their respective owners. April 2007 Revised October 2008 ...
Page 12
Introduction 2 Introduction The Texas Instruments XIO2000A is a PCI Express to PCI local bus translation bridge that provides full PCI Express and PCI local bus functionality and performance. 2.1 Description The XIO2000A is a single-function PCI Express to PCI ...
Page 13
... XIO2000A PCI-Express to PCI Bridge XIO2000A PCI-Express to PCI Bridge XIO2000AI PCI-Express to PCI Bridge XIO2000AI PCI-Express to PCI Bridge XIO2000AI PCI-Express to PCI Bridge April 2007 Revised October 2008 REVISION COMMENTS VOLTAGE 3.3-V, 5.0-V tolerant PCI bus I/Os with 201-terminal GZZ MicroStar 3.3-V and 1.5-V power terminals 3.3-V, 5.0-V tolerant PCI bus I/Os with 201-terminal ZZZ (Lead-Free) 3 ...
Page 14
... Terminal Assignments The XIO2000A is available in either a 201-ball GZZ/ZZZ MicroStar package. The XIO2000AI is available in a 201-ball ZZZ MicroStar BGA or a 175-ball ZHH MicroStar package. Figure 2−1 shows a terminal diagram of the GZZ/ZZZ package, and Table 2−1 lists the GZZ/ZZZ terminals sorted alphanumerically. Figure 2−2 shows a terminal diagram of the ZHH package, and Table 2−2 lists the ZHH package terminals sorted alphanumerically. Figure 2− ...
Page 15
... B AD12 AD10 C/BE[0] AD7 A AD11 AD9 VCCP AD6 Figure 2−1. XIO2000A GZZ MicroStar BGA Package, XIO2000A/XIO2000AI ZZZ MicroStar BGA Package(Bottom View) April 2007 Revised October 2008 GPIO3 GPIO6 GPIO7 RSVD RSVD RSVD GPIO5 // GPIO2 RSVD ...
Page 16
Introduction Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically BGA BALL # SIGNAL NAME A02 AD11 A03 AD9 A04 V CCP A05 AD6 A06 AD4 A07 AD0 A08 GNT0 A09 GNT1 A10 GNT2 A11 CLKOUT3 A12 CLKOUT4 A13 CLKOUT5 A14 GNT5 A15 ...
Page 17
Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically (Continued) BGA BALL # SIGNAL NAME L17 REF1_PCIE M01 AD26 M02 AD27 M03 V DD_33 M15 PME M16 WAKE M17 V DD_15_COMB N01 AD28 N02 AD29 N03 V SS N15 RSVD N16 RSVD N17 ...
Page 18
... C C/BE[1] AD15 AD14 AD8 AD7 B AD13 AD12 AD10 C/BE[0] AD6 A AD11 AD9 VCCP AD5 Figure 2−2. XIO2000A/XIO2000AI ZHH Microstar BGA Package (Bottom View) 8 SCPS155C RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VSS VDD_33 GPIO7 RSVD ...
Page 19
Table 2−2. ZHH Terminals Sorted Alphanumerically BGA BALL # SIGNAL NAME A02 AD11 A03 AD9 A04 V CCP A05 AD5 A06 AD2 A07 AD0 A08 REQ1 A09 CLKOUT2 A10 REQ3 A11 REQ4 A12 REQ5 A13 CLKOUT6 A14 REFCLK_SEL B01 AD13 ...
Page 20
Introduction Table 2−2. ZHH Terminals Sorted Alphanumerically (Continued) BGA BALL # SIGNAL NAME L14 RSVD M01 M66EN M02 INTA M03 INTD M04 GPIO3 M05 GPIO6 M06 RSVD M07 RSVD M08 V SS M09 V DD_33 M10 V DD_33 M11 V ...
Page 21
... SERR PAR 2 IRDY AD11 AD12 AD15 STOP 1 AD13 PERR DEVSEL FRAME Figure 2−3. XIO2000A/XIO2000AI ZHC Microstar BGA Package (Bottom View) April 2007 Revised October 2008 VDD_15 TXP PERST VDD_33_AUX REF0_PCIE VSS TXN VDDA_15 REF1_PCIE VDD_33_ VDD_33_ ...
Page 22
Introduction Table 2−3. ZHC Terminal Names Sorted Alphanumerically BGA BALL # SIGNAL NAME A02 AD11 A03 AD9 A04 AD7 A05 AD4 A06 AD1 A07 AD0 A08 CLKOUT1 A09 CLKOUT2 A10 GNT2 A11 CLKOUT4 A12 GNT4 A13 GNT5 A14 VSSA B01 ...
Page 23
Figure 2−3. ZHC Terminal Names Sorted Alphanumarically (Continued) BGA BALL # SIGNAL NAME L14 WAKE M01 M66EN M02 INTA M03 INTD M04 GPIO0 // CLKRUN M05 GPIO2 M06 GPIO6 M07 RSVD M08 VSS M09 VSS M10 RSVD M11 RSVD M12 ...
Page 24
... Introduction Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically GZZ/ZZZ ZHC SIGNAL NAME BALL # BALL # AD0 A07 A07 AD1 B07 A06 AD2 C07 B06 AD3 D07 C06 AD4 A06 A05 AD5 B06 B05 AD6 A05 C05 AD7 B05 A04 AD8 C04 D05 ...
Page 25
... Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued) GZZ/ZZZ ZHC SIGNAL NAME BALL # BALL # REQ4 B12 B11 REQ5 B13 B12 RSVD D16 D12 RSVD D17 D14 RSVD N15 K12 RSVD N16 L07 RSVD P16 L12 RSVD P17 M07 RSVD R08 M10 ...
Page 26
... Introduction Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued) GZZ/ZZZ ZHC SIGNAL NAME BALL # BALL # V SS G09 V SS G10 V SS G11 V SS H07 V SS H08 V SS H09 V SS H10 V SS H11 V SS J07 V SS J08 V SS J09 V SS J10 V SS J11 ...
Page 27
GZZ/ZZZ ZHC SIGNAL BALL # BALL # V CCP A04, J01 B04, G02 D09, H14, J04, D08, F14, G04, V DD_15 P07, P15 L05, N13 F17, J14, J15, D13, E11, H11, V DDA_15 G15 H13 C06, C13, D10, D04, D06, ...
Page 28
Introduction GZZ/ ZHC ZHH SIGNAL ZZZ BALL # BALL # BALL # PERST J17 H14 H12 REF0_PCIE L16 K14 J14 REF1_PCIE L17 J13 J13 RXP E17 E13 E14 RXN E16 E14 E13 TXP H17 G14 G14 TXN H16 G13 G13 ...
Page 29
GZZ/ZZZ ZHC SIGNAL BALL # BALL # REFCLK_SEL A16 D11 REFCLK+ C17 C14 REFCLK− C16 B14 CLK P03 L03 CLKOUT0 C08 D07 CLKOUT1 B09 A08 CLKOUT2 B10 A09 CLKOUT3 A11 D09 CLKOUT4 A12 A11 CLKOUT5 A13 C10 CLKOUT6 B14 C11 ...
Page 30
Introduction GZZ/ZZZ ZHC SIGNAL BALL # BALL # AD31 P02 L01 AD30 P01 L02 AD29 N02 K03 AD28 N01 K04 AD27 M02 K02 AD26 M01 K01 AD25 L04 J03 AD24 L03 J04 AD23 L01 J01 AD22 K03 H04 AD21 K02 ...
Page 31
Table 2−10. PCI System Terminals (Continued) GZZ/ZZZ ZHC ZHH SIGNAL BALL # BALL # BALL # PAR E02 D03 D02 PERR F03 C01 D03 PME M15 M14 L12 REQ5 B13 B12 A12 REQ4 B12 B11 A11 REQ3 B11 C09 A10 ...
Page 32
Introduction GZZ/ ZHC ZHH I/O SIGNAL ZZZ BALL BALL TYPE BALL CLKRUN_EN B15 B13 B13 EXT_ARB_EN A15 C12 B12 GPIO0 // T05 M04 P03 I/O CLKRUN GPIO1 // U05 P03 P04 I/O PWR_OVRD GPIO2 T06 M05 N04 I/O GPIO3 U06 ...
Page 33
... MHz, then this terminal is connected Note: The XIO2000AI industrial temperature device does not support 66 MHz operation so for the XIO2000AI, this pin must be grounded for proper operation. Serial IRQ interface. This terminal functions as a serial IRQ interface if a pullup is detected when PERST is deasserted ...
Page 34
Feature/Protocol Descriptions 3 Feature/Protocol Descriptions This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the ...
Page 35
See the power-up sequencing diagram in Figure 3−2. V DD_15 and V DDA_15 V DD_33 and V DDA_33 V CCP REFCLK PERST 3.1.2 Power-Down Sequence 1. Assert PERST to the device. 2. Remove the reference clock. 3. Remove V clamp ...
Page 36
Feature/Protocol Descriptions V DD_15 and V DDA_15 V DD_33 and V DDA_33 V CCP REFCLK PERST 3.2 Bridge Reset Features There are five bridge reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets ...
Page 37
RESET OPTION XIO2000A FEATURE Bridge During a power-on cycle, the bridge asserts an internal internally-generated reset and monitors the V DD_15_COMB (M17) terminal. power-on reset When this terminal reaches 90% of the nominal input voltage specification, power is considered stable. ...
Page 38
Feature/Protocol Descriptions If the REFCLK_SEL (A16) input is connected expected by the bridge. If the A16 terminal is connected to V reference is expected by the bridge. When the single-ended, 125-MHz clock reference option is enabled, the ...
Page 39
Table 3−3. Messages Supported by the Bridge MESSAGE Assert_INTx Deassert_INTx PM_Active_State_Nak PM_PME PME_Turn_Off PME_TO_Ack ERR_COR ERR_NONFATAL ERR_FATAL Unlock Set_Slot_Power_Limit Hot plug messages Advanced switching messages Vendor defined type 0 Vendor defined type 1 All supported message transactions are processed per ...
Page 40
Feature/Protocol Descriptions The PCI bus signals attached to the V • In Table 2−9, Clock Terminals, the terminal names include CLK and CLKOUT6:0. • In Table 2−10, PCI System Terminals, all terminal names except for PME • In Table 2−12, ...
Page 41
MSI Messages Generated from the Serial IRQ Interface When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The following ...
Page 42
Feature/Protocol Descriptions The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit memory write transactions. The system message and message number fields are included in bytes 0 and 1 of the data payload. ...
Page 43
PCI Port Arbitration The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. Three options exist when configuring the bridge arbiter for these seven bus devices: classic PCI arbiter, 128-phase, WRR time-based ...
Page 44
Feature/Protocol Descriptions To enable the 128-phase, WRR time-based arbiter, two configuration registers must be written. Bit 1 (PORTARB_LEVEL_1_EN) in the upstream isochrony control register at offset 04h (see Section 6.4) within the device control memory window register map must be ...
Page 45
PCI Express Extended VC With VC Arbitration When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted access to the upstream PCI Express link. These three arbitration modes include strict priority, ...
Page 46
Feature/Protocol Descriptions Table 3−10. 32-phase, WRR Arbiter Registers PCI OFFSET REGISTER NAME Classic PCI configuration General control register D4h (see Section 4.65) PCI Express VC extended Port VC control configuration register 15Ch (see Section 5.19) PCI Express VC extended Port ...
Page 47
Bridge REQ REQ0 REQ1 REQ2 Bridge GNT GNT0 GNT1 GNT2 Isoc Ref Clock Port Arb Table Bridge PCI Bus 3.6 Configuration Register Translation PCI Express configuration register transactions received by the bridge are decoded ...
Page 48
Feature/Protocol Descriptions In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL signal. The implemented IDSEL signal mapping is shown in Table 3−11. Table 3−11. Type 0 Configuration Transaction IDSEL Mapping ...
Page 49
Table 3−12. Interrupt Mapping In The Code Field + Fmt Type Byte 0> Byte 0> Byte 4> Byte 4> Requester ID ...
Page 50
Feature/Protocol Descriptions 3.9 PCI Express To PCI Bus Lock Conversion The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal ...
Page 51
CLK FRAME LOCK AD IRDY TRDY DEVSEL Figure 3−12. Continuing A Locked Sequence Because PCI Express does not have a unique locked-memory write request packet, all PCI Express memory write requests that are received while the bridge is locked are ...
Page 52
Feature/Protocol Descriptions 3.10.1 Serial-Bus Interface Implementation To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for ...
Page 53
SDA SCL Start Condition Figure 3−15. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are transmitted is unlimited. However, each byte must be followed ...
Page 54
Feature/Protocol Descriptions Figure 3−18 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the ...
Page 55
Table 3−13. EEPROM Register Loading Map SERIAL EEPROM WORD ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh ...
Page 56
Feature/Protocol Descriptions 3.10.4 Accessing Serial-Bus Devices Through Software The bridge provides a programming mechanism to control serial-bus devices through system software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−14 lists the registers ...
Page 57
If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data parity error is detected, then this information is passed to the PCI Express interface this, the bridge ...
Page 58
Feature/Protocol Descriptions Table 3−15. Clocking In Low Power States CLOCK SOURCE PCI express reference clock input (REFCLK) PCI clock input (CLK) Secondary PCI bus clock outputs (CLKOUT6:0) The link power management (LPM) state machine manages active state power by monitoring ...
Page 59
Classic PCI Configuration Space The programming model of the XIO2000A PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header. k All bits marked with ...
Page 60
Classic PCI Configuration Space Table 4−1. PCI Express Configuration Register Map (Continued) GPIO data† Reserved Clock run status† Reserved Arbiter time-out status Serial IRQ edge control† Reserved † One or more bits in this register are reset by a PCI ...
Page 61
Command Register The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 RESET STATE ...
Page 62
Classic PCI Configuration Space 4.4 Status Register The status register provides information about the PCI Express interface to the system. See Table 4−3 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER ...
Page 63
Class Code and Revision ID Register This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as ...
Page 64
Classic PCI Configuration Space 4.9 BIST Register Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when read. PCI register offset: Register type: Default value: BIT NUMBER 7 6 RESET ...
Page 65
Secondary Bus Number Register This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected to. The bridge uses this register to determine how to respond to a type 1 configuration transaction. ...
Page 66
Classic PCI Configuration Space 4.16 I/O Limit Register This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See Table 4−7 for a complete description of the register contents. PCI register offset: Register type: ...
Page 67
Secondary Status Register The secondary status register provides information about the PCI bus interface. See Table 4−8 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 RESET STATE 0 ...
Page 68
Classic PCI Configuration Space 4.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4−9 for a complete description of the register contents. PCI register offset: Register type: ...
Page 69
Prefetchable Memory Limit Register This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4−12 for a complete description of the register contents. PCI register offset: Register type: Default value: ...
Page 70
Classic PCI Configuration Space 4.24 I/O Base Upper 16-Bit Register This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete description of the register contents. PCI register offset: Register type: Default ...
Page 71
Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has ...
Page 72
Classic PCI Configuration Space Table 4−17. Bridge Control Register Description (Continued) BIT FIELD NAME ACCESS 9 SEC_DT RW Selects the number of PCI clocks that the bridge waits for a master on the secondary interface to repeat a delayed transaction ...
Page 73
Table 4−17. Bridge Control Register Description (Continued) BIT FIELD NAME ACCESS 2 ISA RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O ...
Page 74
Classic PCI Configuration Space 4.32 Power Management Capabilities Register This read-only register indicates the capabilities of the bridge related to PCI power management. See Table 4−18 for a complete description of the register contents. PCI register offset: Register type: Default ...
Page 75
Power Management Control/Status Register This register determines and changes the current power state of the bridge. No internal reset is generated when transitioning from the D3 register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 ...
Page 76
Classic PCI Configuration Space 4.35 Power Management Data Register The read-only register is not applicable to the bridge and returns 00h when read. PCI register offset: Register type: Default value: BIT NUMBER 7 6 RESET STATE 0 0 4.36 MSI ...
Page 77
MSI Message Control Register This register controls the sending of MSI messages. See Table 4−21 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 RESET STATE 0 0 Table ...
Page 78
Classic PCI Configuration Space 4.40 MSI Message Upper Address Register This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is detected. If this register contains 0000 0000h, then 32-bit ...
Page 79
Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 90h pointing to the PCI Express capabilities registers. PCI register offset: Register type: ...
Page 80
Classic PCI Configuration Space 4.47 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 00h indicating no additional capabilities are supported. PCI register ...
Page 81
Device Capabilities Register The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 31 30 RESET STATE ...
Page 82
Classic PCI Configuration Space 4.50 Device Control Register The device control register controls PCI Express device specific parameters. See Table 4−26 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 ...
Page 83
Table 4−26. Device Control Register Description (Continued) BIT FIELD NAME ACCESS Unsupported request reporting enable. If this bit is set, then the bridge sends an ERR_NONFATAL message to the root complex when an unsupported request is received. 3 URRE RW ...
Page 84
Classic PCI Configuration Space 4.52 Link Capabilities Register The link capabilities register indicates the link specific capabilities of the bridge. See Table 4−28 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER ...
Page 85
Link Control Register The link control register controls link specific behavior. See Table 4−29 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 15 14 RESET STATE 0 0 Table 4−29. ...
Page 86
Classic PCI Configuration Space 4.54 Link Status Register The link status register indicates the current state of the PCI Express link. See Table 4−30 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT ...
Page 87
Serial-Bus Slave Address Register The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this ...
Page 88
Classic PCI Configuration Space 4.58 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial bus. See Table 4−32 for ...
Page 89
GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), ...
Page 90
Classic PCI Configuration Space 4.60 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or is ...
Page 91
Control and Diagnostic Register 0 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−35 for a complete description of the register contents recommended that all values within ...
Page 92
Classic PCI Configuration Space 4.62 Control and Diagnostic Register 1 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−36 for a complete description of the register contents recommended ...
Page 93
Control and Diagnostic Register 2 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4−37 for a complete description of the register contents recommended that all values within ...
Page 94
Classic PCI Configuration Space 4.65 General Control Register This read/write register controls various functions of the bridge. See Table 4−39 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 31 30 RESET ...
Page 95
Table 4−39. General Control Register Description (Continued) BIT FIELD NAME ACCESS Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions. READ_ 19† PREFETCH_ Prefetch to the next cache line boundary on a ...
Page 96
Classic PCI Configuration Space 4.66 Clock Control Register This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER 7 6 ...
Page 97
Clock Mask Register This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the ...
Page 98
Classic PCI Configuration Space 4.68 Clock Run Status Register The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4−42 for a complete description of the register contents. PCI register offset: Register ...
Page 99
Arbiter Control Register The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration tier. See Table ...
Page 100
Classic PCI Configuration Space 4.70 Arbiter Request Mask Register The arbiter request mask register enables and disables support for requests from specific masters on the secondary bus. The arbiter request mask register also controls if a request input is automatically ...
Page 101
Arbiter Time-Out Status Register The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out ...
Page 102
Classic PCI Configuration Space 4.72 Serial IRQ Mode Control Register This register controls the behavior of the serial IRQ controller. See Table 4−46 for a complete description of the register contents. PCI register offset: Register type: Default value: BIT NUMBER ...
Page 103
Serial IRQ Edge Control Register This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 4−47 for a complete description of the register contents. PCI register offset: Register type: Default ...
Page 104
Classic PCI Configuration Space Table 4−47. Serial IRQ Edge Control Register Description (Continued) BIT FIELD NAME ACCESS IRQ 1 edge mode 1† IRQ1_MODE RW IRQ 0 edge mode 0† IRQ0_MODE RW † These bits are reset by a PCI Express ...
Page 105
Table 4−48. Serial IRQ Status Register Description (Continued) BIT FIELD NAME ACCESS IRQ 6 asserted. This bit indicates that the IRQ6 has been asserted. 6 IRQ6 RCU 0 = Deasserted 1 = Asserted IRQ 5 asserted. This bit indicates that ...
Page 106
PCI Express Extended Configuration Space 5 PCI Express Extended Configuration Space The programming model of the PCI Express extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The ...
Page 107
Table 5−1. PCI Express Extended Configuration Register Map (Continued) VC arbitration table (phase 31 − phase 24) Port arbitration table for VC1 (phase 7 – phase 0) Port arbitration table for VC1 (phase 15 – phase 8) Port arbitration table ...
Page 108
PCI Express Extended Configuration Space 5.3 Uncorrectable Error Status Register The uncorrectable error status register reports the status of individual errors as they occur on the primary PCI Express interface. Software may only clear these bits by writing a 1b ...
Page 109
Uncorrectable Error Mask Register The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are ...
Page 110
PCI Express Extended Configuration Space 5.5 Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a ...
Page 111
Correctable Error Status Register The correctable error status register reports the status of individual errors as they occur. Software may only clear these bits by writing the desired location. See Table 5−5 for a complete description ...
Page 112
PCI Express Extended Configuration Space 5.7 Correctable Error Mask Register The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, ...
Page 113
Advanced Error Capabilities and Control Register The advanced error capabilities and control register allows the system to monitor and control the advanced error reporting capabilities. See Table 5−7 for a complete description of the register contents. PCI Express extended ...
Page 114
PCI Express Extended Configuration Space 5.10 Secondary Uncorrectable Error Status Register The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur. Software may only clear these bits by writing the ...
Page 115
Secondary Uncorrectable Error Mask Register The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error ...
Page 116
PCI Express Extended Configuration Space 5.12 Secondary Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When ...
Page 117
Secondary Error Capabilities and Control Register The secondary error capabilities and control register allows the system to monitor and control the secondary advanced error reporting capabilities. See Table 5−11 for a complete description of the register contents. PCI Express ...
Page 118
PCI Express Extended Configuration Space 5.14 Secondary Header Log Register The secondary header log register stores the transaction address and command for the PCI bus cycle that led to the most recently detected error condition. Offset 13Ch accesses register bits ...
Page 119
Next Capability Offset/Capability Version Register This read-only register returns the value 000h to indicate that this extended capability block represents the end of the linked list of extended capability structures. The four least significant bits identify the revision of ...
Page 120
PCI Express Extended Configuration Space 5.18 Port VC Capability Register 2 The second port VC capability register provides information to software regarding the VC arbitration schemes supported by the bridge. See Table 5−14 for a complete description of the register ...
Page 121
Port VC Control Register The port VC control register allows software to configure the VC arbitration options within the bridge. See Table 5−15 for a complete description of the register contents. PCI Express extended register offset: Register type: Default ...
Page 122
PCI Express Extended Configuration Space 5.21 VC Resource Capability Register (VC0) The VC resource capability register for VC0 provides information to software regarding the port and arbitration schemes supported by the bridge. See Table 5−17 for a complete description of ...
Page 123
VC Resource Control Register (VC0) The VC resource control register for VC0 allows software to control VC0 and the associated port and arbitration schemes supported by the bridge. See Table 5−18 for a complete description of the register contents. ...
Page 124
PCI Express Extended Configuration Space 5.23 VC Resource Status Register (VC0) The VC resource status register allows software to monitor the status of the port arbitration table for this VC. See Table 5−19 for a complete description of the register ...
Page 125
VC Resource Control Register (VC1) The VC resource control register for VC1 allows software to control the second VC and associated port and arbitration schemes supported by the bridge. See Table 5−21 for a complete description of the register ...
Page 126
PCI Express Extended Configuration Space 5.26 VC Resource Status Register (VC1) The VC resource status register allows software to monitor the status of the port arbitration table for this VC. See Table 5−22 for a complete description of the register ...
Page 127
Port Arbitration Table (VC1) The port arbitration table is provided to allow software to define round-robin weighting for traffic entering the PCI interface. The table is divided into 128 phases. PCI Express extended register offset: Register type: Default value: ...
Page 128
Memory-Mapped TI Proprietary Register Space 6 Memory-Mapped TI Proprietary Register Space The programming model of the memory-mapped TI proprietary register space is unique to this device. These custom registers are specifically designed to provide enhanced features associated with upstream isochronous ...
Page 129
Revision ID Register The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value 00h identifies the revision as the initial layout. Device control memory window register offset: Register type: Default ...
Page 130
Memory-Mapped TI Proprietary Register Space 6.4 Upstream Isochrony Control Register The upstream isochrony control register allows software to control bridge isochronous behavior. See Table 6−3 for a complete description of the register contents. Device control memory window register offset: Register ...
Page 131
Upstream Isochronous Window 0 Control Register The upstream isochronous window 0 control register allows software to identify the traffic class (TC) associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−4 for ...
Page 132
Memory-Mapped TI Proprietary Register Space 6.8 Upstream Isochronous Window 1 Control Register The upstream isochronous window 1 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See ...
Page 133
Upstream Isochronous Window 2 Control Register The upstream isochronous window 2 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−6 for a complete ...
Page 134
Memory-Mapped TI Proprietary Register Space 6.14 Upstream Isochronous Window 3 Control Register The upstream isochronous window 3 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See ...
Page 135
GPIO Control Register This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), ...
Page 136
Memory-Mapped TI Proprietary Register Space 6.18 GPIO Data Register This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO terminals. Writing to a bit that is in input mode or ...
Page 137
Serial-Bus Word Address Register The value written to the serial-bus word address register represents the word address of the byte being read from or written to on the serial-bus interface. The word address is loaded into this register prior ...
Page 138
Memory-Mapped TI Proprietary Register Space 6.22 Serial-Bus Control and Status Register The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial-bus. This register is an ...
Page 139
Serial IRQ Mode Control Register This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode control register in the classic PCI configuration space (offset E0h, see Section 4.72). See ...
Page 140
Memory-Mapped TI Proprietary Register Space 6.24 Serial IRQ Edge Control Register This register controls the edge mode of each IRQ in the serial IRQ stream. This register is an alias for the serial IRQ edge control register in the classic ...
Page 141
Table 6−13. Serial IRQ Edge Control Register Description (Continued) BIT FIELD NAME ACCESS IRQ 3 edge mode 3† IRQ3_MODE RW IRQ 2 edge mode 2† IRQ2_MODE RW IRQ 1 edge mode 1† IRQ1_MODE RW IRQ 0 edge mode 0† IRQ0_MODE ...
Page 142
Memory-Mapped TI Proprietary Register Space Table 6−14. Serial IRQ Status Register Description (Continued) BIT FIELD NAME ACCESS IRQ 8 asserted. This bit indicates that the IRQ has been asserted. 8 IRQ8 RCU 0 = Deasserted 1 = Asserted IRQ 7 ...
Page 143
... OPERATION 1.5 V 3.3 V 3.3 V 5.0 V XIO2000A (Commercial) XIO2000AI (Industrial) Electrical Characteristics † –0 3.6 V –0 1.65 V –0 5.25 V –0 0.5 V CCP – ...
Page 144
Electrical Characteristics 7.3 Nominal Power Consumption DEVICES POWER STATE No downstream D0 idle One downstream D0 idle One downstream D0 active Two downstream D0 idle Two downstream D0 active NOTES idle power state: Downstream PCI device is in ...
Page 145
PCI Express Differential Transmitter Output Ranges PARAMETER TERMINALS UI TXP, TXN 399.88 Unit interval V TX-DIFFp-p Differential TXP, TXN peak-to-peak output voltage V TX-DE-RATIO De-emphasized TXP, TXN differential output voltage (ratio) T TX-EYE TXP, TXN Minimum TX eye width ...
Page 146
Electrical Characteristics PCI Express Differential Transmitter Output Ranges (continued) PARAMETER TERMINALS I TX-SHORT TXP, TXN TX short circuit current limit T TX-IDLE-MIN TXP, TXN Minimum time spent in electrical idle T TX-IDLE-SET-to-IDLE Maximum time to transition to a valid TXP, ...
Page 147
PCI Express Differential Receiver Input Ranges PARAMETER TERMINALS MIN UI RXP, RXN 399.88 Unit interval V RX-DIFFp-p RXP, RXN 0.175 Differential input peak-to-peak voltage T RX-EYE RXP, RXN Minimum receiver eye width T RX-EYE-MEDIAN-to-MAX- JITTER Maximum time between RXP, ...
Page 148
Electrical Characteristics 13 RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The T RX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution ...
Page 149
PCI Express Differential Reference Clock Input Ranges PARAMETER TERMINALS MIN f IN-DIFF REFCLK+ Differential input REFCLK− frequency f IN-SE REFCLK+ Single-ended input frequency V RX-DIFFp-p REFCLK+ Differential input REFCLK− peak-to-peak voltage V IH-SE REFCLK+ 0.7 V DDA_33 V IL-SE ...
Page 150
Electrical Characteristics 7.7 Electrical Characteristics Over Recommended Operating Conditions (PCI Bus) PARAMETER High-level input voltage (Note 18) High-level input voltage (Note 18 Low-level input voltage (Note 18) Low-level input voltage (Note 18) ...
Page 151
PCI Clock Timing Requirements Over Recommended Operating Conditions PARAMETER PARAMETER t c Cycle time, CLK t wH Pulse duration (width), CLK high t wL Pulse duration (width), CLK low t rise Slew rate, CLK t fall t dc CLKOUT6:0 ...
Page 152
Electrical Characteristics 7.11 PCI Bus Parameter Measurement Information LOAD CIRCUIT PARAMETERS C LOAD † TIMING I OL PARAMETER (pF) (mA) t PZH t en 30/ PZL t PHZ t dis 12 30/50 t PLZ t pd 30/50 12 ...
Page 153
PCI Bus Parameter Measurement Information 0 rise CLK PRST CLK 1.5 V PCI Output PCI Input Figure 7−4. Shared Signals Timing Waveforms April 2007 Revised October 2008 fall t c ...
Page 154
Glossary 8 Glossary ACRONYM DEFINITION BIST Built-in self test ECRC End-to-end cyclic redundancy code EEPROM Electrically erasable programmable read-only memory GP General purpose GPIO General-purpose input output ID Identification IF Interface IO Input output I2S Inter IC sound LPM Link ...
Page 155
... Mechanical Data The XIO2000A/XIO2000AI devices is available in the 175−ball lead−free (Pb atomic number 82) Microstar BGA package (ZHH), the 175-ball lead-free (Pb atomic number 82) MicroStar BGA package ZHC, the 201-ball MicroStar BGA package (GZZ – XIO2000A Only,) or the 201-ball lead-free (Pb atomic number 82) MicroStar BGA package (ZZZ) ...
Page 156
... PACKAGING INFORMATION (1) Orderable Device Status XIO2000AGZZ ACTIVE XIO2000AIZHC PREVIEW XIO2000AIZHH ACTIVE XIO2000AIZZZ ACTIVE XIO2000AZHC PREVIEW XIO2000AZHH ACTIVE XIO2000AZZZ ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...
Page 157
...
Page 158
...
Page 159
...