XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 116

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.12 Secondary Uncorrectable Error Severity Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
106
31:14
BIT
13†
12†
11†
10†
9†
8†
7†
6†
5†
3†
2†
1†
4
0
SCPS155C
The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
cleared, the corresponding error condition is identified as nonfatal. See Table 5−10 for a complete description
of the register contents.
RESET STATE
RESET STATE
SC_MSTR_ABORT_SEVR
BIT NUMBER
BIT NUMBER
DISCARD_TIMER_SEVR
MASTER_ABORT_SEVR
BRIDGE_ERROR_SEVR
TARGET_ABORT_SEVR
SERR_DETECT_SEVR
PERR_DETECT_SEVR
SC_MSG_DATA_SEVR
UNCOR_ADDR_SEVR
UNCOR_DATA_SEVR
PCI Express extended register offset:
Register type:
Default value:
ATTR_ERROR_SEVR
SC_ERROR_SEVR
FIELD NAME
Table 5−10. Secondary Uncorrectable Error Severity Register Description
RSVD
RSVD
RSVD
31
15
0
0
30
14
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
29
13
R
R
R
0
0
28
12
0
1
Reserved. Returns 00 0000 0000 0000 0000b when read.
Internal bridge error. This severity bit is associated with a PCI-X error and has no
effect on the bridge.
SERR assertion detected
PERR assertion detected
Delayed transaction discard timer expired
Uncorrectable address error
Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has
no effect on the bridge.
Uncorrectable data error
Uncorrectable split completion message data error. This severity bit is associated with
a PCI-X error and has no effect on the bridge.
Unexpected split completion error. This severity bit is associated with a PCI-X error
and has no effect on the bridge.
Reserved. Returns 0b when read.
Received master abort
Received target abort
Master abort on split completion. This severity bit is associated with a PCI-X error and
has no effect on the bridge.
Reserved. Returns 0b when read.
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
0 = Error condition is signaled using ERR_NONFATAL
1 = Error condition is signaled using ERR_FATAL (default)
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
0 = Error condition is signaled using ERR_NONFATAL (default)
1 = Error condition is signaled using ERR_FATAL
27
11
0
0
26
10
0
0
134h
Read-only, Read/Write
0000 1340h
25
0
9
1
24
0
8
1
23
0
7
0
DESCRIPTION
22
0
6
1
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0