XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 102

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XIO2000AI

Manufacturer Part Number
XIO2000AI
Description
PCI Express to PCI Bus Translation Bridge
Manufacturer
TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]
Datasheet

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Classic PCI Configuration Space
4.72 Serial IRQ Mode Control Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
92
3:2†
BIT
7:4
1†
0†
SCPS155C
This register controls the behavior of the serial IRQ controller. See Table 4−46 for a complete description of
the register contents.
RESET STATE
BIT NUMBER
START_WIDTH
FIELD NAME
DRIVEMODE
PCI register offset:
Register type:
Default value:
POLLMODE
RSVD
ACCESS
7
0
Table 4−46. Serial IRQ Mode Control Register Description
RW
RW
RW
R
6
0
Reserved. Returns 0h when read.
Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.
Poll mode. This bit selects between continuous and quiet mode.
Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.
5
0
00 = 4 clocks (default)
01 = 6 clocks
10 = 8 clocks
11 = Reserved
0 = Continuous mode (default)
1 = Quiet mode
0 = Drive high (default)
1 = 3-state
E0h
Read-only, Read/Write
00h
4
0
3
0
2
0
1
0
0
0
DESCRIPTION
April 2007 Revised October 2008

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