XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 114

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.10 Secondary Uncorrectable Error Status Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
104
31:14
BIT
13†
12†
11†
10†
9†
8†
7†
6†
5†
3†
2†
1†
4
0
SCPS155C
The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur.
Software may only clear these bits by writing a 1b to the desired location. See Table 5−8 for a complete
description of the register contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
SC_MSTR_ABORT
DISCARD_TIMER
MASTER_ABORT
BRIDGE_ERROR
TARGET_ABORT
SERR_DETECT
PERR_DETECT
SC_MSG_DATA
UNCOR_ADDR
PCI Express extended register offset:
Register type:
Default value:
ATTR_ERROR
UNCOR_DATA
FIELD NAME
SC_ERROR
RSVD
RSVD
RSVD
Table 5−8. Secondary Uncorrectable Error Status Register Description
31
15
0
0
ACCESS
RCU
RCU
RCU
RCU
RCU
RCU
RCU
30
14
0
0
R
R
R
R
R
R
R
R
29
13
0
0
Reserved. Returns 00 0000 0000 0000 0000b when read.
Internal bridge error. This error bit is associated with a PCI-X error and returns 0b when read.
SERR assertion detected. This bit is asserted when the bridge detects the assertion of SERR
on the secondary bus.
PERR assertion detected. This bit is asserted when the bridge detects the assertion of PERR
on the secondary bus.
Delayed transaction discard timer expired. This bit is asserted when the discard timer expires
for a pending delayed transaction that was initiated on the secondary bus.
Uncorrectable address error. This bit is asserted when the bridge detects a parity error during
the address phase of an upstream transaction.
Uncorrectable attribute error. This error bit is associated with a PCI-X error and returns 0b
when read.
Uncorrectable data error. This bit is asserted when the bridge detects a parity error during a
data phase of an upstream write transaction, or when the bridge detects the assertion of
PERR when forwarding read completion data to a PCI device.
Uncorrectable split completion message data error. This error bit is associated with a PCI-X
error and returns 0b when read.
Unexpected split completion error. This error bit is associated with a PCI-X error and returns
0b when read.
Reserved. Returns 0b when read.
Received master abort. This bit is asserted when the bridge receives a master abort on the
PCI interface.
Received target abort. This bit is asserted when the bridge receives a target abort on the PCI
interface.
Master abort on split completion. This error bit is associated with a PCI-X error and returns 0b
when read.
Reserved. Returns 0b when read.
28
12
0
0
27
11
0
0
26
10
0
0
12Ch
Read-only, Read/Clear
0000 0000h
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0