XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 40

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.4.3 PCI Bus Clock Run
3.4.4 PCI Bus External Arbiter
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SCPS155C
The PCI bus signals attached to the V
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The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run
protocol is enabled, the bridge assumes the role of the central resource master.
To enable the clock run function, terminal B15 (CLKRUN_EN) is asserted high. Then, terminal T05 (GPIO0)
is enabled as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal
from floating. To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock
run status register at offset DAh (see Section 4.68) is read.
Since the bridge has several unique features associated with the PCI bus interface, the system designer must
consider the following interdependencies between these features and the CLKRUN feature:
1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the
2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state
3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks,
4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a
5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus
6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream
7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during
The bridge supports an external arbiter for the PCI bus. Terminal A15 (EXT_ARB_EN), when asserted high,
enables the use of an external arbiter.
When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge.
Likewise, REQ0 is connected to the external arbiter as the GNT for the bridge.
All internal port arbitration features are disabled when an external arbiter is enabled. 128-phase, weighted
round-robin (WRR) time-based arbitration, bus parking, arbiter time-out, tier select, and request masking
modes have no effect if an external arbiter is enabled.
In Table 2−9, Clock Terminals, the terminal names include CLK and CLKOUT6:0.
In Table 2−10, PCI System Terminals, all terminal names except for PME
In Table 2−12, Miscellaneous Terminals, the terminal names include SERIRQ, M66EN, and LOCK.
bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN
master and does not support the CLKRUN slave mode.
changes and will generate and send PCI Express messages upstream.
then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks.
minimum of 512 cycles.
clocks running until the IRQ interrupt is cleared by software.
transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus
clocks.
PCI bus resets.
CCP
clamping voltage are identified in the following list:
April 2007 Revised October 2008