XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 71

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.27 Interrupt Line Register
4.28 Interrupt Pin Register
4.29 Bridge Control Register
April 2007 Revised October 2008
15:12
BIT
10
11
This read/write register is programmed by the system and indicates to the software which interrupt line the
bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch
pad register.
The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While
the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the
primary interface.
The bridge control register provides extensions to the command register that are specific to a bridge. See
Table 4−17 for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
FIELD NAME
DTSTATUS
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
DTSERR
RSVD
ACCESS
15
0
RCU
7
1
7
0
RW
R
14
Table 4−17. Bridge Control Register Description
0
6
1
6
0
Reserved. Returns 0h when read.
Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the bridge to
generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary
interface when the secondary discard timer expires and a delayed transaction is discarded from a
queue in the bridge. The severity is selectable only if advanced error reporting is supported.
Discard timer status. This bit indicates if a discard timer expires and a delayed transaction is
discarded.
0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of
1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the secondary
0 = No discard timer error
1 = Discard timer error
13
0
5
1
5
0
the expiration of the secondary discard timer. Note that an error message can still be sent if
advanced error reporting is supported and bit 10 (DISCARD_TIMER_MASK) in the
secondary uncorrectable error mask register (offset 130h, see Section 5.11) is clear
(default).
discard timer expires and a delayed transaction is discarded from a queue in the bridge
3Ch
Read/Write
FFh
3Dh
Read-only
00h
3Eh
Read-only, Read/Write, Read/Clear
0000h
12
0
4
1
4
0
11
0
3
1
3
0
10
0
2
1
2
0
9
0
1
1
1
0
8
0
DESCRIPTION
0
1
0
0
7
0
6
0
5
0
Classic PCI Configuration Space
4
0
3
0
SCPS155C
2
0
1
0
0
0
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