XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 69

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.21 Prefetchable Memory Limit Register
4.22 Prefetchable Base Upper 32-Bit Register
4.23 Prefetchable Limit Upper 32-Bit Register
April 2007 Revised October 2008
15:4
31:0
31:0
BIT
BIT
BIT
3:0
This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4−12 for a complete description of the register contents.
This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 4−13
for a complete description of the register contents.
This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4−14
for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
FIELD NAME
FIELD NAME
FIELD NAME
PREBASE
PCI register offset:
Register type:
Default value:
PRELIMIT
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PRELIMIT
64BIT
Table 4−13. Prefetchable Base Upper 32-Bit Register Description
Table 4−14. Prefetchable Limit Upper 32-Bit Register Description
ACCESS
ACCESS
ACCESS
Table 4−12. Prefetchable Memory Limit Register Description
15
31
15
31
15
0
0
0
0
0
RW
RW
RW
R
14
30
14
30
14
0
0
0
0
0
Prefetchable memory limit. Defines the highest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.23) specifies bits
[63:32] of the 64-bit prefetchable memory address.
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
13
29
13
29
13
0
0
0
0
0
26h
Read-only, Read/Write
0001h
28h
Read/Write
0000 0000h
2Ch
Read/Write
0000 0000h
12
28
12
28
12
0
0
0
0
0
27
27
11
11
11
0
0
0
0
0
10
26
10
26
10
0
0
0
0
0
25
25
9
0
0
9
0
0
9
0
24
24
8
0
0
8
0
0
8
0
DESCRIPTION
DESCRIPTION
DESCRIPTION
23
23
7
0
0
7
0
0
7
0
22
22
6
0
0
6
0
0
6
0
21
21
5
0
0
5
0
0
5
0
Classic PCI Configuration Space
20
20
4
0
0
4
0
0
4
0
19
19
3
0
0
3
0
0
3
0
SCPS155C
18
18
2
0
0
2
0
0
2
0
17
17
1
0
0
1
0
0
1
0
16
16
0
1
0
0
0
0
0
0
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