XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 59

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4
April 2007 Revised October 2008
Classic PCI Configuration Space
The programming model of the XIO2000A PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI
bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.
All bits marked with a
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
† One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Secondary latency timer
Serial-bus control and
PM data
status†
BIST
PCI Express capabilities register
Power management capabilities
Prefetchable memory limit
I/O limit upper 16 bits
MSI message control
Secondary status
Subsystem ID†
Bridge control
Device status
Memory limit
Link status
Device ID
Reserved
Reserved
Status
Table 4−1. Classic PCI Configuration Register Map
k
are sticky bits and are reset by a global reset (GRST) or the internally-generated
Serial-bus slave address†
Subordinate bus number
PMCSR_BSE
Header type
Class code
Reserved
Prefetchable base upper 32 bits
Prefetchable limit upper 32 bits
MSI upper message address
Device control base address
MSI message address
REGISTER NAME
Device capabilities
Link capabilities
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Serial-bus word address†
Secondary bus number
Next item pointer
Next item pointer
Next item pointer
Next item pointer
Latency timer
Interrupt pin
I/O limit
Prefetchable memory base
Power management CSR
Subsystem vendor ID†
I/O base upper 16 bits
MSI message data
Device control
Memory base
Link control
Command
Vendor ID
PCI Express capability ID
SSID/SSVID CAP ID
Primary bus number
Capabilities pointer
Serial-bus data†
Cache line size
Interrupt line
MSI CAP ID
Classic PCI Configuration Space
Revision ID
PM CAP ID
I/O base
SCPS155C
0A4h−0ACh
040h−04Ch
058h−05Ch
070h−07Ch
088h−08Ch
OFFSET
00Ch
01Ch
02Ch
03Ch
06Ch
09Ch
0A0h
0B0h
000h
004h
008h
010h
014h
018h
020h
024h
028h
030h
034h
038h
050h
054h
060h
064h
068h
080h
084h
090h
094h
098h
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