XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 96

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.66 Clock Control Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
86
BIT
6†
5†
4†
3†
2†
1†
0†
7
SCPS155C
This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete
description of the register contents.
RESET STATE
CLOCK6_DISABLE
CLOCK5_DISABLE
CLOCK4_DISABLE
CLOCK3_DISABLE
CLOCK2_DISABLE
CLOCK1_DISABLE
CLOCK0_DISABLE
BIT NUMBER
PCI register offset:
Register type:
Default value:
FIELD NAME
RSVD
7
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
R
Table 4−40. Clock Control Register Description
6
0
Reserved. Returns 0b when read.
Clock output 6 disable. This bit disables secondary CLKOUT6.
Clock output 5 disable. This bit disables secondary CLKOUT5.
Clock output 4 disable. This bit disables secondary CLKOUT4.
Clock output 3 disable. This bit disables secondary CLKOUT3.
Clock output 2 disable. This bit disables secondary CLKOUT2.
Clock output 1 disable. This bit disables secondary CLKOUT1.
Clock output 0 disable. This bit disables secondary CLKOUT0.
5
0
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
0 = Clock enabled (default)
1 = Clock disabled
D8h
Read-only, Read/Write
00h
4
0
3
0
2
0
1
0
0
0
DESCRIPTION
April 2007 Revised October 2008