XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 121

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.19 Port VC Control Register
5.20 Port VC Status Register
April 2007 Revised October 2008
15:4
15:1
BIT
BIT
3:1
0
0
The port VC control register allows software to configure the VC arbitration options within the bridge. See
Table 5−15 for a complete description of the register contents.
The port VC status register allows software to monitor the status of the VC arbitration table. See Table 5−16
for a complete description of the register contents.
RESET STATE
RESET STATE
FIELD NAME
VC_TABLE_STATUS
BIT NUMBER
BIT NUMBER
LOAD_VC
_SELECT
PCI Express extended register offset:
Register type:
Default value:
VC_ARB
PCI Express extended register offset:
Register type:
Default value:
_TABLE
RSVD
FIELD NAME
RSVD
ACCESS
RW
RW
15
15
0
0
R
ACCESS
Table 5−15. Port VC Control Register Description
14
14
Table 5−16. Port VC Status Register Description
RU
0
0
R
Reserved. Returns 000h when read.
VC arbitration select. This read/write field allows software to define the mechanism used for VC
arbitration by the bridge. The value written to this field indicates the bit position within bits 7:0
(VC_ARB_CAP) in the port VC capability register 2 (offset 158h, see Section 5.18) that corresponds
to the selected arbitration scheme. Values that may be written to this field include:
All other values are reserved for arbitrations schemes that are not supported by the bridge.
Load VC arbitration table. When software writes a 1b to this bit, the bridge applies the values written
in the VC arbitration table within the extended configuration space to the actual VC arbitration tables
used by the device for arbitration. This bit always returns 0b when read.
000 = Hardware-fixed round-robin (default)
001 = WRR with 32 phases
13
13
0
0
Reserved. Returns 000 0000 0000 0000b when read.
VC arbitration table status. This bit is automatically set by hardware when any modification is
made to the VC arbitration table entries within the extended configuration space. This bit is
cleared by hardware after software has requested a VC arbitration table refresh and the
refresh has been completed.
12
12
0
0
11
11
0
0
10
10
0
0
15Ch
Read-only, Read/Write
0000h
15Eh
Read-only
0000h
9
0
9
0
8
0
8
0
DESCRIPTION
DESCRIPTION
7
0
7
0
PCI Express Extended Configuration Space
6
0
6
0
5
0
5
0
4
0
4
0
3
0
3
0
SCPS155C
2
0
2
0
1
0
1
0
0
0
0
0
111