XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 37

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

3.3
3.3.1 External Reference Clock
April 2007 Revised October 2008
PCI Express reset input
PCI Express training
internally-generated
Global reset input
RESET OPTION
control hot reset
power-on reset
PCI bus reset
PERST (J17)
GRST (N17)
PRST (U03)
PCI Express Interface
The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock
reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for
frequency tolerance, spread spectrum clocking, and signal electrical characteristics.
Bridge
During a power-on cycle, the bridge asserts an internal
reset and monitors the V DD_15_COMB (M17) terminal.
When this terminal reaches 90% of the nominal input
voltage specification, power is considered stable. After
stable power, the bridge monitors the PCI Express
reference clock (REFCLK) and waits 10 µs after active
clocks are detected. Then, internal power-on reset is
deasserted.
When GRST is asserted low, an internal power-on
reset occurs. This reset is asynchronous and functions
during both normal power states and V AUX power
states.
This bridge input terminal is used by an upstream PCI
Express device to generate a PCI Express reset and to
signal a system power good condition.
When PERST is asserted low, the bridge generates an
internal PCI Express reset as defined in the PCI
Express specification.
When PERST transitions from low to high, a system
power good condition is assumed by the bridge.
Note: The system must assert PERST before power is
removed, before REFCLK is removed, or before
REFCLK becomes unstable.
The bridge responds to a training control hot reset
received on the PCI Express interface. After a training
control hot reset, the PCI Express interface enters the
DL_DOWN state.
System software has the ability to assert and deassert
the PRST terminal on the secondary PCI bus interface.
This terminal is the PCI bus reset.
XIO2000A FEATURE
Table 3−1. Bridge Reset Options
When the internal power-on reset is asserted, all
control registers, state machines, sticky register bits,
and power management state machines are initialized
to their default state.
In addition, the bridge asserts PCI bus reset (PRST).
When GRST is asserted low, all control registers, state
machines, sticky register bits, and power management
state machines are initialized to their default state.
In addition, the bridge asserts PCI bus reset (PRST).
When the rising edge of GRST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after GRST is deasserted.
When PERST is asserted low, all control register bits
that are not sticky are reset. Within the configuration
register maps, the sticky bits are indicated by the
symbol. Also, all state machines that are not
associated with sticky functionality or V AUX power
management are reset.
In addition, the bridge asserts PCI bus reset (PRST).
When the rising edge of PERST occurs, the bridge
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after PERST is deasserted.
In the DL_DOWN state, all remaining configuration
register bits and state machines are reset. All
remaining bits exclude sticky bits and EEPROM
loadable bits. All remaining state machines exclude
sticky functionality, EEPROM functionality, and V AUX
power management.
Within the configuration register maps, the sticky bits
are indicated by the
loadable bits are indicated by the † symbol.
In addition, the bridge asserts PCI bus reset (PRST).
When bit 6 (SRST) in the bridge control register at
offset 3Eh (see Section 4.29) is asserted, the bridge
asserts the PRST terminal. A 0 in the SRST bit
deasserts the PRST terminal.
RESET RESPONSE
k
symbol and the EEPROM
Feature/Protocol Descriptions
SCPS155C
k
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