XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 129

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

6.2
6.3
April 2007 Revised October 2008
15:4
BIT
3:0
Revision ID Register
The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value
00h identifies the revision as the initial layout.
Upstream Isochrony Capabilities Register
The upstream isochronous capabilities register provides software information regarding the capabilities
supported by this bridge. See Table 6−2 for a complete description of the register contents.
ISOC_WINDOW_COUNT
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
FIELD NAME
RSVD
Table 6−2. Upstream Isochronous Capabilities Register Description
15
0
7
0
14
0
6
0
ACCESS
R
R
13
0
5
0
Reserved. Returns 000h when read.
Isochronous window count. This 4-bit field indicates the number of isochronous address
windows supported. The value 0100b indicates that 4 separate windows are supported
by the bridge.
12
0
4
0
11
0
3
0
10
0
2
0
9
0
1
0
01h
Read-only
00h
02h
Read-only
0004h
8
0
0
0
Memory-Mapped TI Proprietary Register Space
7
0
DESCRIPTION
6
0
5
0
4
0
3
0
SCPS155C
2
1
1
0
0
0
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