XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 128

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Memory-Mapped TI Proprietary Register Space
6
† One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.1
118
Serial-bus control and status†
SCPS155C
Upstream isochrony capabilities
Memory-Mapped TI Proprietary Register Space
The programming model of the memory-mapped TI proprietary register space is unique to this device. These
custom registers are specifically designed to provide enhanced features associated with upstream
isochronous applications.
All bits marked with a
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST,
GRST, or the internally-generated power-on reset.
Device Control Map ID Register
The device control map ID register identifies the TI proprietary layout for this device control map. The value
01h identifies this as a PCI Express-to-PCI bridge supporting upstream isochronous capabilities.
RESET STATE
BIT NUMBER
Device control memory window register offset:
Register type:
Default value:
Reserved
Reserved
Reserved
Reserved
Reserved
Serial IRQ edge control†
GPIO data†
Reserved
7
0
Table 6−1. Device Control Memory Window Register Map
Serial-bus slave address†
k
Upstream isochronous window 0 base address
Upstream isochronous window 1 base address
Upstream isochronous window 2 base address
Upstream isochronous window 3 base address
are sticky bits and are reset by a global reset (GRST) or the internally-generated
6
0
Upstream isochronous window 0 limit
Upstream isochronous window 1 limit
Upstream isochronous window 2 limit
Upstream isochronous window 3 limit
5
0
REGISTER NAME
4
0
Reserved
Revision ID
3
0
Upstream isochronous window 0 control
Upstream isochronous window 1 control
Upstream isochronous window 2 control
Upstream isochronous window 3 control
Serial-bus word address†
2
0
Upstream isochrony control
Reserved
1
0
00h
Read-only
01h
0
1
Serial IRQ status
GPIO control†
Device control map ID
Serial IRQ mode control†
Serial-bus data†
April 2007 Revised October 2008
38h−3Ch
OFFSET
0Ch
1Ch
2Ch
4Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
40h
44h
48h