XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 81

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.49 Device Capabilities Register
April 2007 Revised October 2008
31:28
27:26
25:18
17:15
11:9
BIT
8:6
4:3
2:0
14
13
12
5
The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a
complete description of the register contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
FIELD NAME
EP_L0S_LAT
EP_L1_LAT
PCI register offset:
Register type:
Default value:
CSPLS
CSPLV
RSVD
RSVD
MPSS
ETFS
ABP
PFS
PIP
AIP
ACCESS
31
15
0
0
RU
RU
RU
RU
R
R
R
R
R
R
R
R
Table 4−25. Device Capabilities Register Description
30
14
0
0
Reserved. Returns 0h when read.
Captured slot power limit scale. The value in this field is programmed by the host by issuing a
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8 are
written to this field. The value in this field specifies the scale used for the slot power limit.
Captured slot power limit value. The value in this field is programmed by the host by issuing a
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0 are
written to this field. The value in this field in combination with the slot power limit scale value
(bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated by
multiplying the value in this field by the value in the slot power limit scale field.
Reserved. Returns 000b when read.
Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not
implemented.
Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not
implemented.
Attention button present. This bit is hardwired to 0b indicating that an attention button is not
implemented.
Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a
transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY field
(bits 15:13) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 32 µs to 64 µs. This field cannot be programmed to be
less than the latency for the PHY to exit the L1 state.
Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a
transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY field
(bits 18:16) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 2 µs to 4 µs. This field cannot be programmed to be less
than the latency for the PHY to exit the L0s state.
Extended tag field supported. This field indicates the size of the tag field not supported.
Phantom functions supported. This field is read-only 00b indicating that function numbers are not
used for phantom functions.
Maximum payload size supported. This field indicates the maximum payload size that the device
can support for TLPs. This field is encoded as 010b indicating the maximum payload size for a TLP
is 512 bytes.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
29
13
0
0
94h
Read-only
0000 0D82
28
12
0
0
27
11
0
1
26
10
0
1
25
0
9
0
24
0
8
1
DESCRIPTION
23
0
7
1
22
0
6
0
21
0
5
0
Classic PCI Configuration Space
20
0
4
0
19
0
3
0
SCPS155C
18
0
2
0
17
0
1
1
16
0
0
0
71