XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 139

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

6.23 Serial IRQ Mode Control Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
3:2†
BIT
7:4
1†
0†
This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ mode
control register in the classic PCI configuration space (offset E0h, see Section 4.72). See Table 6−12 for a
complete description of the register contents.
RESET STATE
BIT NUMBER
START_WIDTH
FIELD NAME
DRIVEMODE
Device control memory window register offset:
Register type:
Default value:
POLLMODE
RSVD
ACCESS
Table 6−12. Serial IRQ Mode Control Register Description
7
0
RW
RW
RW
R
6
0
Reserved. Returns 0h when read.
Start frame pulse width. Used to set the width of the start frame for a SERIRQ stream.
Poll mode. This bit selects between continuous and quiet mode.
Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.
5
0
00 = 4 clocks (default)
01 = 6 clocks
10 = 8 clocks
11 = Reserved
0 = Continuous mode (default)
1 = Quiet mode
0 = Drive high (default)
1 = Tri-state
4
0
3
0
2
0
1
0
48h
Read-only, Read/Write
00h
0
0
DESCRIPTION
Memory-Mapped TI Proprietary Register Space
SCPS155C
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