XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 50

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.9
40
SCPS155C
PCI Express To PCI Bus Lock Conversion
The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is
provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal is a dedicated output
that is enabled by setting bit 12 in the general control register at offset D4h. See Section 4.65, General Control
Register, for details.
PCI Express locked-memory read request transactions are treated the same as PCI Express memory read
transactions except that the bridge returns a completion for a locked-memory read. Also, the bridge uses the
PCI LOCK protocol when initiating the memory read transaction on the PCI bus.
When a PCI Express locked-memory read request transaction is received and the bridge is not already locked,
the bridge arbitrates for use of the LOCK terminal by asserting REQ. If the bridge receives GNT and the LOCK
terminal is high, then the bridge drives the LOCK terminal low after the address phase of the first
locked-memory read transaction to take ownership of LOCK. The bridge continues to assert LOCK except
during the address phase of locked transactions. If the bridge receives GNT and the LOCK terminal is low,
then the bridge deasserts its REQ and waits until LOCK is high and the bus is idle before re-arbitrating for the
use of LOCK.
Once the bridge has ownership of LOCK, the bridge initiates the lock read as a memory read transaction on
the PCI bus. When the target of the locked-memory read returns data, the bridge is considered locked and
all transactions not associated with the locked sequence are blocked by the bridge.
NOTE:The use of LOCK is only supported by PCI-Express to PCI Bridges in the downstream
direction (away from the root complex).
DEVSEL
FRAME
LOCK
TRDY
IRDY
CLK
AD
Figure 3−11. Starting A Locked Sequence
Address
Data
April 2007 Revised October 2008