XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 92

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.62 Control and Diagnostic Register 1
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
82
20:18†
17:15†
14:11†
32:21
9:6†
5:2†
1:0†
BIT
10†
SCPS155C
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
RESET STATE
RESET STATE
L1_EXIT_LAT_
L1_EXIT_LAT_
SBUS_RESET
BIT NUMBER
BIT NUMBER
FIELD NAME
L0s_TIMER
COMMON
PCI register offset:
Register type:
Default value:
L1ASPM_
ASYNC
_MASK
TIMER
RSVD
RSVD
RSVD
ACCESS
31
15
Table 4−36. Control and Diagnostic Register 1 Description
0
0
RW
RW
RW
RW
RW
RW
RW
R
30
14
0
0
Reserved. Returns 000h when read.
L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,
see Section 4.53) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the
link capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the link
capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6
(SRST) of the bridge control register (offset 3Eh, see Section 4.29). This bit defaults to 0b.
L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer. This
field defaults to 0100b.
L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer. This
field defaults to 0010b.
Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00b.
29
13
0
0
C4h
Read/Write
0012 0108h
28
12
0
0
27
11
0
0
26
10
0
0
25
0
9
0
24
0
8
1
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
1
4
0
19
0
3
1
18
0
2
0
17
1
1
0
16
0
0
0