XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 86

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.54 Link Status Register
4.55 Serial-Bus Data Register
4.56 Serial-Bus Word Address Register
76
15:13
BIT
9:4
3:0
12
11
10
SCPS155C
The link status register indicates the current state of the PCI Express link. See Table 4−30 for a complete
description of the register contents.
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the
bus cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY)
of the serial-bus control and status register (offset B3h, see Section 4.58) is cleared. This register is reset by
a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
The value written to the serial-bus word address register represents the word address of the byte being read
from or written to the serial-bus device. The word address is loaded into this register prior to writing the
serial-bus slave address register (offset B2h, see Section 4.57) that initiates the bus cycle. This register is reset
by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
FIELD NAME
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
RSVD
SCC
NLW
TE
LT
LS
ACCESS
15
0
7
0
7
0
R
R
R
R
R
R
14
0
6
0
6
0
Table 4−30. Link Status Register Description
Reserved. Returns 000b when read.
Slot clock configuration. This bit indicates that the bridge uses the same physical reference clock
that the platform provides on the connector. If the bridge uses an independent clock irrespective of
the presence of a reference on the connector, then this bit must be cleared.
Link training. This bit has no function and is read-only 0b.
Retrain link. This bit has no function and is read-only 0b.
Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1x.
Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.
0 = Independent 125-MHz reference clock is used
1 = Common 100-MHz reference clock is used
13
0
5
0
5
0
A2h
Read-only
X011h
B0h
Read/Write
00h
B1h
Read/Write
00h
12
x
4
0
4
0
11
0
3
0
3
0
10
0
2
0
2
0
9
0
1
0
1
0
8
0
DESCRIPTION
0
0
0
0
7
0
6
0
5
0
April 2007 Revised October 2008
4
1
3
0
2
0
1
0
0
1