XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 61

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.3
April 2007 Revised October 2008
15:11
BIT
10
9
8
7
6
5
4
3
2
1
0
Command Register
The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a
complete description of the register contents.
RESET STATE
BIT NUMBER
MEMORY_ENB
MASTER_ENB
INT_DISABLE
FIELD NAME
PCI register offset:
Register type:
Default value:
SERR_ENB
PERR_ENB
STEP_ENB
VGA_ENB
MWI_ENB
FBB_ENB
SPECIAL
IO_ENB
RSVD
15
ACCESS
0
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
14
0
Table 4−2. Command Register Description
Reserved. Returns 00000b when read.
INTx disable. This bit enables device specific interrupts. Since the bridge does not generate any
internal interrupts, this bit is read-only 0b.
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
therefore, this bit returns 0b when read.
SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the PCI
Express interface on behalf of SERR assertions detected on the PCI bus.
Address/data stepping control. The bridge does not support address/data stepping, and this bit is
hardwired to 0b.
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4) in
response to a received poisoned TLP from PCI Express. A received poisoned TLP is forwarded
with bad parity to conventional PCI regardless of the setting of this bit.
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore, this bit
returns 0b when read.
Memory write and invalidate enable. When this bit is set, the bridge translates PCI Express
memory write requests into memory write and invalidate transactions on the PCI interface.
Special cycle enable. The bridge does not respond to special cycle transactions; therefore, this
bit returns 0b when read.
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on the PCI
Express interface.
Memory space enable. Setting this bit enables the bridge to respond to memory transactions on
the PCI Express interface.
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the PCI
Express interface.
13
0
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
0 = PCI Express interface cannot initiate transactions. The bridge must disable the response
1 = PCI Express interface can initiate transactions. The bridge can forward memory and I/O
0 = PCI Express receiver cannot process downstream memory transactions and must
1 = PCI Express receiver can process downstream memory transactions. The bridge can
0 = PCI Express receiver cannot process downstream I/O transactions and must respond
1 = PCI Express receiver can process downstream I/O transactions. The bridge can forward
04h
Read-only, Read/Write
0000h
to memory and I/O transactions on the PCI interface (default).
transactions from PCI secondary interface to the PCI Express interface.
respond with an unsupported request (default)
forward memory transactions to the PCI interface.
with an unsupported request (default)
I/O transactions to the PCI interface.
12
0
11
0
10
0
9
0
8
0
DESCRIPTION
7
0
6
0
5
0
Classic PCI Configuration Space
4
0
3
0
SCPS155C
2
0
1
0
0
0
51