XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 46

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.5.4 128-Phase, WRR PCI Port Arbitration Timing
36
Classic PCI configuration
register D4h
PCI Express VC extended
configuration register 15Ch
PCI Express VC extended
configuration register 15Eh
PCI Express VC extended
configuration registers 180h
to 18Ch
SCPS155C
This section includes a timing diagram that illustrates the 128-phase, WRR time-based arbiter timing for the
bridge and three PCI bus devices. This timing diagram assumes aggressive mode since the transfer
associated with device #1 is stopped to start a device #0 transfer. The PCI bus cycle where device #1 is
stopped is indicated by the ‡ symbol. Device #1 then waits until its next port arbitration table cycle to finish
the transfer.
The signal waveforms associated with bridge REQ, bridge GNT, ISOC reference clock, and port arbitration
table entry are internal to the bridge. These internal bridge signals are included here to help clarify the
operation of the PCI port arbiter in 128-phase, WRR time-based arbitration mode. The remaining REQ, GNT,
and PCI bus signals are all external to the bridge.
PCI OFFSET
General control
(see Section 4.65)
Port VC control
(see Section 5.19)
Port VC status
(see Section 5.20)
VC arbitration table
(see Section 5.27)
REGISTER NAME
Table 3−10. 32-phase, WRR Arbiter Registers
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Bit 0 (LOAD_VC_TABLE) when written with a 1b transfers the VC arbitration table
configuration register values to the internal registers used by the VC arbiter.
Bits 3:1 (VC_ARB_SELECT) equal to 001b enables 32-phase, WRR arbitration
mode.
Bit 0 (VC_TABLE_STATUS) equal to 1b indicates that the VC arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
4-doubleword sized configuration registers that are the registered version of the
32-phase, WRR VC arbitration table. Each VC arbitration table entry is a 4-bit field.
DESCRIPTION
April 2007 Revised October 2008