XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 67

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.17 Secondary Status Register
April 2007 Revised October 2008
10:9
BIT
4:0
15
14
13
12
11
8
7
6
5
The secondary status register provides information about the PCI bus interface. See Table 4−8 for a complete
description of the register contents.
RESET STATE
TABORT_REC
BIT NUMBER
TABORT_SIG
FIELD NAME
PCI_SPEED
SYS_ERR
PCI register offset:
Register type:
Default value:
PAR_ERR
DATAPAR
FBB_CAP
MABORT
66MHZ
RSVD
RSVD
ACCESS
15
0
RCU
RCU
RCU
RCU
RCU
RCU
R
R
R
R
R
Table 4−8. Secondary Status Register Description
14
0
Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data
error by the bridge on its secondary interface. This bit must be set when any of the following three
conditions are true:
•
•
•
The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh
(see Section 4.29).
Received system error. This bit is set when the bridge detects an SERR assertion.
Received master abort. This bit is set when the PCI interface of the bridge reports the detection of
a master abort termination by the bridge when it is the master of a transaction on its secondary
interface.
Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.
Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when
it responds as the target of a transaction on its secondary interface.
DEVSEL timing. These bits are 01b indicating that this is a medium speed decoding device.
Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI
bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.29) is set, and the
bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.
Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI
interface of bridge supports fast back-to-back transactions.
Reserved. Returns 0b when read.
66-MHz capable. The bridge can operate at a maximum CLK frequency of 66 MHz; therefore, this
bit reflects the state of the M66EN terminal.
Reserved. Returns 00000b when read.
0 = Uncorrectable address, attribute, or data error not detected on secondary interface
1 = Uncorrectable address, attribute, or data error detected on secondary interface
0 = No error asserted on the PCI interface
1 = SERR asserted on the PCI interface
0 = Master abort not received on the PCI interface
1 = Master abort received on the PCI interface
0 = Target abort not received on the PCI interface
1 = Target abort received on the PCI interface
0 = Target abort not signaled on the PCI interface
1 = Target abort signaled on the PCI interface
0 = No data parity error detected on the PCI interface
1 = Data parity error detected on the PCI interface
13
The bridge detects an uncorrectable address or attribute error as a potential target.
The bridge detects an uncorrectable data error when it is the target of a write transaction.
The bridge detects an uncorrectable data error when it is the master of a read transaction
(immediate read data).
0
1Eh
Read-only, Read/Clear
02X0h
12
0
11
0
10
0
9
1
8
0
DESCRIPTION
7
1
6
0
5
x
Classic PCI Configuration Space
4
0
3
0
SCPS155C
2
0
1
0
0
0
57