XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 149

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

7.6
NOTE 17: The XIO2000A is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. These
April 2007 Revised October 2008
f IN-DIFF
Differential input
frequency
f IN-SE
Single-ended input
frequency
V RX-DIFFp-p
Differential input
peak-to-peak voltage
V IH-SE
V IL-SE
V RX-CM-ACp
AC peak common
mode input voltage
Duty cycle
Z RX-DIFF-DC
DC differential input
impedance
Z RX-DC
DC input impedance
PARAMETER
PCI Express Differential Reference Clock Input Ranges
system jitter models are described in the PCI-Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO2000A in a
system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
TERMINALS
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK+
REFCLK−
REFCLK−
REFCLK−
REFCLK−
REFCLK−
REFCLK−
0.7 V DDA_33
MIN
0.175
40%
0
NOM
100
125
20
20
0.3 V DDA_33
V DDA_33
MAX
1.200
60%
140
UNITS
MHz
MHz
mV
kΩ
kΩ
V
V
V
The input frequency is 100 MHz + 300 ppm and
− 2800 ppm including SSC-dictated variations.
The input frequency is 125 MHz ± 300 ppm.
V RX-DIFFp-p = 2*|V REFCLK+ − V REFCLK− |
Single-ended, reference clock mode high-level
input voltage
Single-ended, reference clock mode low-level
input voltage
V RX-CM-ACp = RMS( |V REFCLK+ + V REFCLK− |/2 –
V RX-CM-DC )
V RX-CM-DC = D C (avg) of | V REFCLK+ + V REFCLK− |/2
Differential and single-ended waveform input
duty cycle
REFCLK+/− dc differential mode impedance
REFCLK+ dc single-ended mode impedance
COMMENTS
Electrical Characteristics
SCPS155C
139