XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 55

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

April 2007 Revised October 2008
This format must be explicitly followed for the bridge to correctly load initialization values from a serial
EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally
hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the
EEPROM are tied to V
(Figure 3−14) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to
the chip, and the sample application shows these terminal inputs tied to V
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may
be monitored to verify a successful download.
SERIAL EEPROM
WORD ADDRESS
0Ah
0Bh
0Ch
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
1Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
12h
13h
14h
15h
16h
17h
18h
19h
1Fh
20h
11h
SS
Table 3−13. EEPROM Register Loading Map
to achieve this address. The serial EEPROM in the sample application circuit
PCI-Express to PCI bridge function indicator (00h)
PCI CAh, control and diagnostic register 2 byte 2
PCI CBh, control and diagnostic register 2 byte 3
PCI C0h, control and diagnostic register 0 byte 0
PCI C1h, control and diagnostic register 0 byte 1
PCI C2h, control and diagnostic register 0 byte 2
PCI C3h, control and diagnostic register 0 byte 3
PCI C4h, control and diagnostic register 1 byte 0
PCI C5h, control and diagnostic register 1 byte 1
PCI C6h, control and diagnostic register 1 byte 2
PCI C7h, control and diagnostic register 1 byte 3
PCI C8h, control and diagnostic register 2 byte 0
PCI C9h, control and diagnostic register 2 byte 1
PCI E2h, serial IRQ edge control, byte 0
PCI E3h, serial IRQ edge control, byte 1
PCI 84h, subsystem vendor ID, byte 0
PCI 85h, subsystem vendor ID, byte 1
Number of bytes to download (1Eh)
PCI E0h, serial IRQ mode control
PCI D4h, general control, byte 0
PCI D5h, general control, byte 1
PCI D6h, general control, byte 2
PCI D7h, general control, byte 3
PCI 86h, subsystem ID, byte 0
PCI 87h, subsystem ID, byte 1
PCI DDh, arbiter request mask
Reserved—no bits loaded
Reserved—no bits loaded
Reserved—no bits loaded
End-of-list indicator (80h)
PCI DCh, arbiter control
BYTE DESCRIPTION
PCI D8h, clock control
PCI D9h, clock mask
SS
.
Feature/Protocol Descriptions
SCPS155C
45