XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 43

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

3.5.1 PCI Port Arbitration
3.5.1.1
3.5.1.2
April 2007 Revised October 2008
Classic PCI configuration
register DCh
Classic PCI configuration
register DDh
Classic PCI configuration
register DEh
PCI OFFSET
The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. Three options
exist when configuring the bridge arbiter for these seven bus devices: classic PCI arbiter, 128-phase, WRR
time-based arbiter, and 128-phase, WRR aggressive time-based arbiter.
The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3−5
identifies and describes the registers associated with classic PCI arbitration mode.
The 128-phase, WRR time-based arbiter is configured through the PCI express VC extended configuration
space at offset 150h and the device control memory window register map.
The 128-phase, WRR time-based arbiter periodically asserts GNT to a PCI master device based on entries
within a port arbitration table. There are actually two port arbitration tables within the bridge. The first table
is accessed through the PCI Express VC extended configuration register space using configuration read/write
transactions. The second table is internal and is used by the PCI bus arbiter to make GNT decisions. A
configuration register load function exists to transfer the contents of the configuration register table to the
internal table.
The port arbitration table uses a 4-bit field to identify the secondary bus master that receives GNT during each
phase of the time-based WRR arbitration. For the arbiter to recognize a bus master REQ and to generate GNT,
software must allocate at least three consecutive phases to the same port number.
Table 3−6 defines the mapping relationship of the PCI bus devices to a port number in the port arbitration table.
PORT NUMBER
Classic PCI Arbiter
128-Phase, WRR Time-Based Arbiter
0111b−1111b
0000b
0001b
0010b
0100b
0101b
0011b
0110b
Arbiter control
(see Section 4.69)
Arbiter request mask
(see Section 4.70)
Arbiter time-out status
(see Section 4.71)
REGISTER NAME
Internal GNT for PCI master state machine
External GNT0
External GNT1
External GNT2
External GNT3
External GNT4
External GNT5
Reserved
Table 3−6. Port Number to PCI Bus Device Mapping
Table 3−5. Classic PCI Arbiter Registers
Contains a two-tier priority scheme for the bridge and six PCI bus devices. The bridge
defaults to the high priority tier. The six PCI bus devices default to the low priority tier. A
bus parking control bit (bit 7, PARK) is provided.
Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7
(ARB_TIMEOUT) in the arbiter request mask register enables generating timeout
status if a PCI device does not respond within 16 PCI bus clocks. Bit 6 (AUTO_MASK)
in the arbiter request mask register automatically masks a PCI bus REQ if the device
does not respond after GNT is issued. The AUTO_MASK bit is cleared to disable any
automatically generated mask.
When bit 7 (ARB_TIMEOUT) in the arbiter request mask register (see Section 4.70) is
asserted, timeout status for each PCI bus device is reported in this register.
GNT
Internal REQ from PCI master state machine
External REQ0
External REQ1
External REQ2
External REQ3
External REQ4
External REQ5
−
DESCRIPTION
PCI DEVICE
Feature/Protocol Descriptions
SCPS155C
33