HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 752

IC SUPERH MPU ROMLESS 208LQFP

HD6417709SF133B

Manufacturer Part Number
HD6417709SF133B
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417709SF133B

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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23.3.8
Table 23.8 Peripheral Module Signal Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module
TMU,
RTC
SCI
Port
DMAC
Note: * Pcyc is the P clock cycle.
Rev. 5.00, 09/03, page 706 of 760
Peripheral Module Signal Timing
Item
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Oscillation settling time
Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time (clock
synchronization)
Receive data hold time (clock
synchronization)
RTS delay time
CTS setup time (clock synchronization)
CTS hold time (clock synchronization)
Output data delay time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
DREQ setup time
DREQ hold time
DRAK delay time
Edge specification
Both edge specification
Asynchronization
Clock synchronization
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCLKS
TCKS
TCKWH
TCKWL
ROSC
SCYC
SCKR
SCKF
SCKW
TXD
RXS
RXH
RTSD
CTSS
CTSH
PORTD
PORTS1
PORTH1
PORTS2
PORTH2
PORTS3
PORTH3
DRQS
DREQH
DRAKD
Min
15
15
1.5
2.5
3
4
6
0.4
100
100
100
100
15
8
tcyc +
15
8
3
+ 15
8
6
4
tcyc
Max
1.5
1.5
0.6
100
100
17
10
Unit
ns
Pcyc
s
Pcyc * 23.50
tscyc
ns
ns
ns
Figure
23.47
23.48
23.49
23.51
23.50
23.51
23.52
23.53
23.54

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